Stabilization in device characteristics of a bipolar transistor that is included in a semiconductor device with a CMOSFET

Abstract

In the manufacturing process of a Bi-CMOS semiconductor device, which includes a CMOSFET and a bipolar transistor, the steps for forming a well region, source regions, and drain regions of the CMOSFET are also used for forming the bipolar transistor. One of the steps is used for introducing impurities of the same conductivity type in a surface of a base region of the bipolar transistor in order to form a high impurity concentration region in the surface. The high impurity concentration region is formed such that the distance between an emitter region of the bipolar transistor and the high impurity concentration region becomes 1 to 2 μm. The shift in device characteristics of the bipolar transistor is improved by the high impurity concentration region even if the impurity concentration is relatively low at the surface of the base region of the bipolar transistor.

1 . A method for manufacturing a semiconductor device, which includes a CMOSFET and a bipolar transistor, wherein the bipolar transistor is formed on a substrate using steps of forming a well region of the CMOSFET and pairs of regions of the CMOSFET, each pair of which includes a source region and a drain region, on the substrate, and wherein a high impurity concentration region is formed by introducing a first impurity of the same conductivity type as a base region of the bipolar transistor in a surface of the base region.  
   
   
       2 . The method in  claim 1 , wherein the base region is formed using the step of forming the well region, wherein an emitter region of the bipolar transistor is formed by introducing a second impurity at the step of forming one of the pairs of regions, wherein the high impurity concentration region is formed using the step of forming another one of the pairs of regions.  
   
   
       3 . The method in  claim 2 , wherein a self alignment mask pattern of the bipolar transistor is formed using a step of forming a gate electrode of the CMOSFET such that the self alignment mask pattern is located above a surface of the base region between the emitter region and the high impurity concentration region, and wherein the first and second impurities are introduced using the self alignment mask pattern as a mask material.  
   
   
       4 . The method in  claim 1 , wherein the base region is formed using the step of forming the well region, wherein an emitter region of the bipolar transistor is formed by introducing a second impurity, wherein an insulating film is formed on a surface of the bipolar transistor, wherein an emitter support area is formed using a step of forming a gate electrode of the CMOSFET such that the emitter support area is in electric contact with the emitter region and extends out of the emitter region on the insulating film by a predetermined distance, and wherein the first impurity is introduced using the emitter support area as a mask material.  
   
   
       5 . The method in  claim 1 , wherein an emitter region of the bipolar transistor is formed by introducing a second impurity, and wherein the high impurity concentration region and the emitter region are formed such that a distance between the high impurity concentration region and the emitter region is 2 μm or shorter.  
   
   
       6 . The method in  claim 5 , wherein the high impurity concentration region is formed such that the distance is 1 μm or longer.  
   
   
       7 . The method in  claim 1 , wherein the semiconductor device further includes a DCMOSFET, wherein the base region is formed using the step of forming the well region, wherein the high impurity concentration region is formed using a step of forming a region for channel of the DCMOSFET, and wherein an emitter region of the bipolar transistor is formed by introducing a second impurity in a surface of the high impurity concentration region at the step of forming one of the pairs of regions.  
   
   
       8 . The method in  claim 1 , wherein the high impurity concentration region is formed to surround an emitter region of the bipolar transistor.  
   
   
       9 . The method in  claim 1 , wherein the surface of the base region is exposed to ultraviolet rays to reduce the amount of charges existing at an interface between the base region and an insulating film, which is located on the surface of the base region.  
   
   
       10 - 12 . (Cancelled)  
   
   
       13 . A method for manufacturing a semiconductor device, which includes a CMOSFET and a bipolar transistor, wherein the bipolar transistor is formed on a substrate using steps of forming a well region of the CMOSFET and pairs of regions of the CMOSFET, each pair of which includes a source region and a drain region, on the substrate, wherein a base region of the bipolar transistor is formed using the step of forming the well region, wherein a high impurity concentration region is formed by introducing a first impurity of the same conductivity type as the base region in a surface of the base region using the step of forming one of the pairs of regions, wherein an emitter region of the bipolar transistor is formed by introducing a second impurity at the step of forming another one of the pairs of regions, and wherein the high impurity concentration region and the emitter region are formed such that a distance between the high impurity concentration region and the emitter region is 2 μm or shorter.  
   
   
       14 . A method for manufacturing a semiconductor device, which includes a CMOSFET and a bipolar transistor, wherein the bipolar transistor is formed on a substrate using steps of forming a well region of the CMOSFET and pairs of regions of the CMOSFET, each pair of which includes a source region and a drain region, on the substrate, and wherein a surface of a base region of the bipolar transistor is exposed to ultraviolet rays to reduce the amount of charges existing at an interface between the base region and an insulating film, which is located on the surface of the base region.  
   
   
       15 . The method in  claim 14 , wherein the semiconductor device further includes an EPROM, and wherein a passivation film, which is transparent to ultraviolet rays, is formed on the CMOSFET, the bipolar transistor, and the EPROM before the step of exposing.  
   
   
       16 - 17 . (Cancelled).  
   
   
       18 . The method in  claim 14 , wherein an SOI substrate is used for the substrate.  
   
   
       19 . A method for manufacturing a semiconductor device, which includes a CMOSFET and a bipolar transistor, wherein the bipolar transistor is formed on a substrate using steps of forming a well region of the CMOSFET and pairs of regions of the CMOSFET, each pair of which includes a source region and a drain region, on the substrate, and wherein an insulating film is formed on a surface of a base region of the bipolar transistor, and wherein a hydrogen barrier film is formed on the insulating film to cover the surface of the base region.  
   
   
       20 - 21 . (Cancelled)  
   
   
       22 . The method in  claim 19 , wherein the base region is formed using the step of forming the well region, wherein an emitter region of the bipolar transistor is formed by introducing a second impurity, wherein an emitter support area is formed as the hydrogen barrier film using a step of forming a gate electrode of the CMOSFET such that the emitter support area is in electric contact with the emitter region and extends out of the emitter region by a predetermined distance.  
   
   
       23 . The method in  claim 19 , wherein the hydrogen barrier film is formed using a portion of metal electrode of the bipolar transistor.  
   
   
       24 . The method in  claim 23 , wherein the metal electrode is a base electrode.  
   
   
       25 . The method in  claim 23 , wherein the metal electrode is an emitter electrode.  
   
   
       26 . The method in  claim 19 , wherein the hydrogen barrier film is formed from a silicon nitride film.  
   
   
       27 . (Cancelled)  
   
   
       28 . A semiconductor device comprising a CMOSFET and a bipolar transistor, wherein the CMOSFET and the bipolar transistor are located on the same substrate, wherein a high impurity concentration region, which includes a impurity of the same conductivity type as a base region of the bipolar transistor with higher concentration than the base region, is located in a surface of the base region.  
   
   
       29 . The semiconductor device in  claim 28 , wherein the high impurity concentration region has substantially the same impurity concentration as a pair of regions that includes a source region and a drain region of the CMOSFET.  
   
   
       30 . The semiconductor device in  claim 29  further comprising a self alignment mask pattern that is used to adjust the distance between an emitter region of the bipolar transistor and the high impurity concentration region to a predetermined distance in a manufacturing process of the semiconductor device.  
   
   
       31 . The semiconductor device in  claim 28 , wherein the bipolar transistor includes an insulating film, wherein the insulating film is located on a surface of the base region, wherein the emitter support area is in electric contact with an emitter region of the bipolar transistor and extends on the insulating film by a predetermined dimension, and wherein the emitter support area is used as a mask material for forming the high impurity concentration region in a manufacturing process of the semiconductor device.  
   
   
       32 - 33 . (Cancelled)  
   
   
       34 . The semiconductor device in  claim 28 , wherein the semiconductor device further comprises a DMOSFET, and wherein the high impurity concentration region has substantially the same impurity concentration as a region for channel of the DCMOSFET.  
   
   
       35 . The semiconductor device in  claim 28 , wherein the high impurity concentration region is located to surround an emitter region of the bipolar transistor.  
   
   
       36 . The semiconductor device in  claim 28 , wherein a hydrogen barrier film is located on a surface of the base region with an insulating film in-between.  
   
   
       37 . The method in  claim 36 , wherein the hydrogen barrier film includes one film selected from the group that consists of a polycrystalline silicon film, an aluminum film, and a silicon nitride film.  
   
   
       38 . The semiconductor device in  claim 28 , wherein the substrate is an SOI substrate.  
   
   
       39 . A semiconductor device comprising a CMOSFET and a bipolar transistor, wherein the CMOSFET and the bipolar transistor are located on the same substrate, wherein a hydrogen barrier film is located on a surface of the base region with an insulating film in-between.  
   
   
       40 - 41 . (Cancelled)  
   
   
       42 . The semiconductor in  claim 39 , wherein the bipolar transistor includes an emitter support area, wherein the emitter support area is in electric contact with an emitter region of the bipolar transistor and extends on the insulating film by a predetermined dimension to function as the hydrogen barrier film.  
   
   
       43 . The semiconductor in  claim 39 , wherein the hydrogen barrier film is a portion of a metal electrode of the bipolar transistor.  
   
   
       44 . The semiconductor device in  claim 43 , wherein the metal electrode is a base electrode.  
   
   
       45 . The semiconductor device of  claim 43 , wherein the metal electrode is an emitter electrode.  
   
   
       46 . The semiconductor device in  claim 39 , wherein the hydrogen barrier film is a silicon nitride film.  
   
   
       47 . (Cancelled)