Method for manufacturing a semiconductor device and semiconductor device with overlay mark

Abstract

In a method for forming a semiconductor device and a semiconductor device having an overlay mark, a first pattern for the semiconductor device is formed in a semiconductor device formation region of a semiconductor substrate and simultaneously in a first mark formation region of the semiconductor substrate. A second pattern for the semiconductor device is formed on a resultant structure in the semiconductor device formation region of the semiconductor substrate and simultaneously in a second mark formation region of the semiconductor substrate. The first and second patterns in the first and second mark formation regions, respectively, are inspected for misalignments using overlay marks formed to have shapes and sizes identical to those of real patterns in the semiconductor device formation region of the semiconductor substrate. By measuring misalignments of real patterns using the overlay marks, overlay mismatch between the semiconductor device formation region and the overlay mark may be prevented.

1 - 5 . (Cancelled)  
   
   
       6 . A semiconductor device having an overlay mark, the overlay mark, comprising: 
 a first mark formed in a first mark formation region of a semiconductor substrate and a first pattern formed in a semiconductor device formation region of the semiconductor substrate, wherein the first mark and the first pattern are formed simultaneously by a same process such that the first mark has a shape identical to a shape of the first pattern; and    a second mark formed in a second mark formation region of the semiconductor substrate and a second pattern formed in the semiconductor device formation region of the semiconductor substrate, wherein the second mark and the second pattern are formed simultaneously by a same process such that the second mark has a shape identical to a shape of the second pattern.    
   
   
       7 . The semiconductor device as claimed in  claim 6 , wherein the first mark formation region is a box shaped main scale formation region, and the second mark formation region is a box shaped vernier formation region.  
   
   
       8 . The semiconductor device as claimed in  claim 7 , wherein the first pattern is an active pattern in a DRAM cell region, and the second pattern is a word line pattern in the DRAM cell region.