Thin film transistor array substrate for liquid crystal display and method for fabricating the same

Abstract

In a method of fabricating a thin film transistor array substrate, a black matrix with horizontal and vertical portions is first formed on a substrate with an opaque conductive material. A gate line assembly is formed on the black matrix, and buffer layers are formed between the separate portions of the black matrix. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially deposited onto the substrate. And a data line assembly is formed on the ohmic contact layer. The ohmic contact layer exposed through the data line assembly is etched, and a protective layer is deposited onto the substrate. The protective layer, the gate insulating layer, and the semiconductor layer are patterned to form contact holes and opening portions exposing the insulating layer at pixel areas. The peripheral portions of the black matrix are also exposed through the opening portions. An indium tin oxide layer is deposited onto the substrate, and patterned to form pixel electrodes, subsidiary gate pads and subsidiary data pads that are connected to the drain electrodes, the gate pads and the data pads through the contact holes. Buffer conductive layers are formed at the same plane as the data line assembly or the pixel electrodes while being positioned over the semiconductor pattern between the neighboring data lines. Opening portions may be formed at a common electrode of the color filter substrate over the semiconductor pattern.

1 - 25 . (Cancelled)  
   
   
       26 . A liquid crystal display (LCD), comprising: 
 a first insulating substrate;    a black matrix formed on the first substrate, the black matrix being mesh-shaped and having a plurality of opening portions at pixel areas;    an insulating layer formed on the first substrate and the black matrix;    a gate line assembly formed on the insulating layer and comprising a plurality of gate lines and a plurality of gate electrodes;    a gate insulating layer formed on the gate line assembly;    a semiconductor layer formed on the gate insulating layer;    an ohmic contact layer formed on the semiconductor layer;    a data line assembly formed on the ohmic contact layer and comprising a plurality of source electrodes, a plurality of drain electrodes and a plurality of data lines, the data lines intersecting the gate lines to define the pixel areas;    a protective layer formed on the data line assembly and the gate line assembly and having a plurality of first contact holes exposing the drain electrodes; and    a plurality of pixel electrodes connected to the drain electrodes through the first contact holes, respectively.    
   
   
       27 . The LCD of  claim 26 , wherein the protective layer has the same shape as the gate insulting layer and the semiconductor layer except for the first contact holes.  
   
   
       28 . The LCD of  claim 26 , wherein the black matrix overlaps edges of the protective layer, the gate insulating layer, and the semiconductor layer except for areas where the drain electrodes are located.  
   
   
       29 . The LCD of  claim 26 , wherein the gate line assembly further comprises a plurality of gate pads, and the data line assembly further comprises a plurality of data pads, and 
 the LCD further comprises:    a plurality of second contact holes extending through the gate insulating layer, the semiconductor layer and the protective layer and exposing the gate pads;    a plurality of third contact holes formed through the protective layer and exposing the data pads; and    a plurality of subsidiary gate pads formed on the gate pads; and    a plurality of subsidiary data pads formed on the data pads,    wherein the subsidiary gate pads and the subsidiary data pads are derived from the same layer as the pixel electrodes.    
   
   
       30 . The LCD of  claim 29 , wherein the protective layer has the same shape as the gate insulating layer and the semiconductor layer except for the first contact holes and the third contact holes.  
   
   
       31 . The LCD of  claim 26 , further comprising a plurality of buffer conductive patterns formed over the semiconductor layer between the neighboring data lines, the buffer conductive patterns derived from the same layer as the pixel electrodes.  
   
   
       32 . The LCD of  claim 31 , wherein the buffer conductive patterns are connected to the gate line assembly.  
   
   
       33 . The LCD of  claim 26 , further comprising: 
 a plurality of buffer conductive patterns formed on the semiconductor layer between the neighboring data lines;    a plurality of second contact holes exposing the gate lines and the buffer conductive patterns; and    a plurality of connection patterns connecting the gate lines to the buffer conductive patterns though the second contact holes, the connection pattern derived from the same layer as the pixel electrodes.    
   
   
       34 . A method for fabricating a thin film transistor substrate, comprising steps of: 
 forming a black matrix on an insulating substrate, the black matrix being mesh shaped and having opening portions at pixel areas;    forming an insulating layer on the black matrix;    forming a gate line assembly on the insulating layer, the gate line assembly comprising a plurality of gate lines and a plurality of gate electrodes connected to the gate lines, respectively;    forming a gate insulating layer on the gate line assembly;    forming a semiconductor layer on the gate insulating layer;    forming an ohmic contact layer on the semiconductor layer;    forming a data line assembly on the ohmic contact layer, the data line assembly comprising a plurality of source electrodes, a plurality of drain electrodes and a plurality of data lines, the data lines intersecting the gate lines to define the pixel areas;    depositing a protective layer covering the data line assembly and the gate line assembly;    forming a plurality of first contact holes extending through the protective layer, the gate insulating layer and the semiconductor layer and exposing the drain electrodes; and    forming a plurality of pixel electrodes connected to the drain electrodes through the first contact holes.    
   
   
       35 . The method of  claim 34 , wherein the protective layer has the same shape as the gate insulating layer and the semiconductor layer except for the first contact holes.  
   
   
       36 . The method of  claim 34 , wherein the black matrix overlaps edges of the protective layer, the gate insulating layer and the semiconductor layer except for areas where the drain electrodes are located.  
   
   
       37 . The method of  claim 34 , wherein the gate line assembly further comprises a plurality of gate pads, and the data line assembly further comprises a plurality of data pads, and 
 the method further comprises steps of:    forming a plurality of second contact holes extending through the gate insulating layer, the semiconductor layer and the protective layer and exposing the gate pads;    forming a plurality of third contact holes extending through the gate insulating layer, the semiconductor layer and the protective layer and exposing the data pads; and    forming a plurality of subsidiary gate pads and a plurality of subsidiary data pads on the gate pads and the data pads, respectively.    
   
   
       38 . The method of  claim 37 , wherein the protective layer has the same shape as the gate insulating layer and the semiconductor layer except for the first contact holes and the third contact holes.  
   
   
       39 . The method of  claim 34 , the step of forming the plurality of pixel electrodes comprising a step of forming buffer conductive patterns over the semiconductor layer between the neighboring data lines.  
   
   
       40 . The method of  claim 34 , the step of forming the plurality of pixel electrodes comprising steps of: 
 forming a plurality of buffer conductive patterns over the semiconductor layer between the neighboring data lines, the protective layer having a plurality of second contact holes exposing the gate lines and the buffer conductive patterns; and    forming a connection layer connecting the gate lines to the buffer conductive patterns through the second contact holes.