Method and system for writing data to a memory

Abstract

Methods and systems consistent with this invention write data to a memory. Such methods and systems may generate a clock signal, generate an intermediate clock signal from the clock signal using a clock tree buffer, delay the intermediate clock signal to form a data strobe signal, and write the data to the memory using the data strobe signal and a memory clock signal. Such methods and systems may also delay the intermediate clock signal to form the memory clock signal.

1 - 20 . (Canceled)  
   
   
       21 . A controller circuit for writing data to a memory, the controller circuit comprising: 
 a first data channel to carry data from the controller circuit to the memory;    a second data channel to carry data from the controller circuit to the memory; and    a first delay circuit to delay the data in the first data channel so that the data in the first data channel is latched into the memory at a different time than the data in the second data channel.    
   
   
       22 . The circuit of  claim 21 , further comprises a second delay circuit to generate a data strobe signal and a third delay circuit to generate a memory clock signal, wherein the data strobe signal and the memory clock signal are used to latch the data into the memory.  
   
   
       23 . The circuit of  claim 22 , wherein the first delay circuit further comprises a first selecting circuit to select a plurality of data clock signals of different phases as an input clock signal for latching the data into the memory.  
   
   
       24 . The circuit of  claim 22 , wherein the first delay circuit further comprises a second selecting circuit to select at least one of a plurality of phase-shifted signals as an output.  
   
   
       25 . The circuit of  claim 22 , wherein the second delay circuit further comprises a third selecting circuit to select at least one of a plurality of phase-shifted signals as an output.  
   
   
       26 . A method for writing data to a memory, the method comprising: 
 delaying data in a first data channel so that the data in the first data channel is latched into the memory at a different time than data in a second data channel, wherein the first data channel carries the data from a controller circuit to the memory and the second data channel carries the data from the controller circuit to the memory.    
   
   
       27 . The method of  claim 26 , further comprises generating a data strobe signal by a first delay circuit and generating a memory clock signal by a second delay circuit wherein the data strobe signal and the memory clock signal are used to latch the data into the memory.  
   
   
       28 . The method of  claim 26 , wherein delaying data in the first data channel further comprises selecting from a plurality of data clock signals of different phases as an inputclock signal for latching the data into the memory.  
   
   
       29 - 54 . (Canceled)