Fabrication process for a semiconductor device having a metal oxide dielectric material with a high dielectric constant, annealed with a buffered anneal process

Abstract

A method of forming an annealed high-K metal oxide transistor gate structure is disclosed. A metal oxide layer is formed over a semiconductor substrate. The metal oxide layer undergoes a buffered annealed process in an oxygen atmosphere to anneal the metal oxide layer at or below the thermodynamic chemical equilibrium of SiO/SiO 2 and at or above the thermodynamic chemical equilibrium of the metal oxide layer.

1 - 18 . (Cancelled)  
   
   
       19 . A high dielectric constant gate structure for use in a transistor, said gate structure comprising: 
 a semiconductor substrate;    an annealed metal oxide dielectric layer provided over said substrate, wherein said annealed metal oxide dielectric layer has a fixed charge of greater than approximately 10 10 /cm 2  and less than approximately 10 12 /cm 2 ; and,    a gate conductor provided over said annealed metal oxide dielectric layer.    
   
   
       20 . The structure as in  claim 19 , wherein said metal oxide dielectric layer comprises a layer selected from the group consisting of a unary, binary, and ternary metal oxide layer.  
   
   
       21 . The structure as in  claim 19 , wherein said metal oxide dielectric layer has a fixed charge of approximately 10 11 /cm 2 .  
   
   
       22 . The structure as in  claim 19 , further comprising an interfacial layer provided between said annealed metal oxide dielectric layer and said substrate, said interfacial layer comprising a material selected from the group consisting of silicon dioxide, silicon oxynitride, and a chemically-prepared silicon oxide.