US2005056916A1PendingUtilityA1

Circuit device and manufacturing method of circuit device

Assignee: SANYO ELECTRIC CO LTD A JAPANPriority: Jan 31, 2000Filed: Aug 13, 2004Published: Mar 17, 2005
Est. expiryJan 31, 2020(expired)· nominal 20-yr term from priority
H10W 72/552H10W 74/00H10W 70/40H10W 72/0198H10W 72/884H10W 72/5449H10W 72/5363H10W 90/754H10W 72/5524H10W 72/5522H10W 72/59H10W 72/536H10W 90/756H10W 72/932H10W 90/00H10W 72/07533H10W 72/952H10W 72/075H10W 72/074H10W 72/07336H10W 72/354H10W 72/325H10W 72/352H10W 72/20H10W 72/07251H10W 90/736H10W 90/734H10P 72/7438H10W 74/111H10W 74/01H10W 70/042H10W 70/04H05K 1/187H05K 3/06H05K 3/202H05K 1/188H05K 1/18
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Claims

Abstract

After a trench 54 is formed in a conductive foil 60, the circuit elements are mounted, and the insulating resin is applied on the conductive foil 60 as the support substrate. After being inverted, the conductive foil 60 is polished on the insulating resin 50 as the support substrate for separation into the conductive paths. Accordingly, it is possible to fabricate the circuit device in which the conductive paths 51 and the circuit elements 52 are supported by the insulating resin 50, without the use of the support substrate. And the interconnects L 1 to L 3 requisite for the circuit are formed, and can be prevented from slipping because of the curved structure 59 and a visor 58.

Claims

exact text as granted — not AI-modified
1 - 46 . (Canceled)  
   
   
       47 . A method of manufacturing a circuit device using a conductive plate having a trench that separates conductive path regions of the conductive plate, wherein the trench has a depth less than the thickness of the conductive plate, the method comprising: 
 planarly mounting a plurality of circuit elements on a conductive path to make a electrical circuit.    
   
   
       48 . The method of  claim 47  wherein including mounting a circuit element over said trench.  
   
   
       49 . The method of  claim 47  wherein the conductive plate is a partially etched or pressed metal plate.  
   
   
       50 . The method of  claim 49  wherein the circuit element comprises a semiconductor chip.  
   
   
       51 . The method of  claim 49  wherein the trench has a thickness in a range of 20-100 μm.  
   
   
       52 . The method of  claim 49  including filling the trench with an insulating resin.  
   
   
       53 . The method of  claim 52  including removing part of the conductive plate from a side of the conductive plate opposite the resin-filled trench to a depth that reaches the resin-filled trench so that the conductive paths are electrically isolated from one another.  
   
   
       54 . The method of  claim 53  including removing part of the conductive plate so that a back side of the conductive paths protrudes beyond a back side of the resin-filled trench.  
   
   
       55 . The method of  claim 53  including removing a part of the conductive plate so that a back side of the resin-filled trench protrudes beyond a back side of the conductive paths.  
   
   
       56 . A method of manufacturing a circuit device using a conductive plate having a resin-filled trench that separates conductive path regions of the conductive plate, wherein the resin-filled trench has a depth less than the thickness of the conductive plate, and wherein the conductive path regions provide electrical connections among a plurality of circuit elements, the method comprising: 
 removing part of the conductive plate from a side of the conductive plate opposite the resin-filled trench to a depth that reaches the resin-filled trench so that the conductive paths are isolated from one another.    
   
   
       57 . The method of  claim 56  including removing part of the conductive plate so that a back side of the conductive paths protrudes beyond a back side of the resin-filled trench.  
   
   
       58 . The method of  claim 56  including removing part of the conductive plate so that a back side of the resin-filled trench protrudes beyond a back side of the conductive paths  
   
   
       59 . The method of  claim 56  wherein the conductive plate is a partially etched or pressed metal plate.  
   
   
       60 . The method of  claim 59  wherein the circuit element comprises a semiconductor chip.  
   
   
       61 . The method of  claim 60  wherein the trench has a thickness in a range of 20-100 μm.  
   
   
       62 . A method of manufacturing a circuit device using a conductive plate having one or more trenches that separate die pad regions, bonding pad regions and interconnection regions of the conductive plate, wherein the one or more trenches have a depth less than the thickness of the conductive plate, the method comprising: 
 providing an electrical connection between a circuit element and one of the bonding pad regions; and    providing an insulating resin to cover the die pad regions, the bonding pad regions, the interconnection regions, the electrical connection and the circuit element, and to fill the one or more trenches.    
   
   
       63 . The method of  claim 62  including: 
 etching a back side of the interconnection regions to expose the resin-filled one or more trenches.    
   
   
       64 . The method of  claim 62  wherein at least one of the interconnection regions interconnects one of the die pad regions to at least one of the bonding pad regions.  
   
   
       65 . A method of manufacturing a circuit device, the method comprising: 
 providing a conductive plate; and    partially etching or pressing a front side of the conductive plate to form die pad regions, bonding pad regions, and interconnection regions in the conductive plate,    wherein each interconnection region electrically couples a respective first die pad or bonding pad region to a respective second die pad or bonding pad region.    
   
   
       66 . The method of  claim 65  wherein at least one of the interconnection regions interconnects one of the die pad regions to at least one of the bonding pad regions.  
   
   
       67 . The method of  claim 65  including: 
 mounting a circuit element on a surface of at least one of the die pad regions;    providing an electrical connection between the circuit element and at least one of the bonding pad regions; and    providing an insulating resin over the front side of the conductive plate, wherein the insulating resin fills areas between the die pad regions, the bonding pad regions and the interconnection regions.    
   
   
       68 . The method of  claim 67  including: 
 removing part of the conductive plate from a side of the conductive plate opposite the side of the conductive plate on which the insulating resin is provided to a depth that reaches the resin-filled areas.    
   
   
       69 . The method of  claim 68  including removing part of the conductive plate so that a back side of the die pad regions, the bonding pad regions and the interconnection regions protrudes beyond a back side of the resin-filled areas.  
   
   
       70 . A circuit device comprising: 
 a die pad region, bonding pad regions, and an interconnection region, wherein the interconnection region electrically couples a first bonding pad region to a second bonding pad region or the die pad region;    a circuit element mounted on a surface of the die pad region; and    an insulating resin ( 50 ) over circuit element, wherein the insulating resin fills areas between the die pad region, the bonding pad regions and the interconnection region.    
   
   
       71 . A circuit device comprising 
 first and a second die pads region; and    an interconnection region,    wherein the interconnection region extends in parallel with and in a vicinity of a side of the first die pad region up to and in parallel with a vicinity of a side of the second die pad region, and wherein the interconnection region functions as an interconnection between a bonding pad of a first circuit element mounted on the first die pad region, a bonding pad of a second circuit element mounted on the second die pad region, and the first and second bonding pads,    and including an insulating resin over the die pad regions, the bonding pad regions and the interconnection region, wherein the insulating resin fills areas between the die pad regions, the bonding pad regions and the interconnection region.    
   
   
       72 . The circuit device of  claim 71  comprising a semiconductor element mounted on a surface of at least one of the die pad regions, and including an interconnection region that extends from at least one the die pad regions.  
   
   
       73 . The circuit device of  claim 71  comprising a first transistor chip mounted on a surface of a first one of the die pad regions and a second transistor chip mounted on a surface of a second one of the die pad regions, 
 wherein the first transistor chip is electrically coupled to a first one of the bonding pad regions that serves as a first emitter electrode, and the second transistor chip is electrically coupled to a second one of the bonding pad regions that serves as a second emitter electrode,    wherein an interconnection region interconnects the first and second bonding pad regions.    
   
   
       74 . The circuit device of  claim 71  comprising a first transistor chip mounted on a surface of a first one of the die pad regions and a second transistor chip mounted on a surface of a second one of the die pad regions, 
 wherein the first transistor chip is electrically coupled to a first one of the bonding pad regions that serves as a first base electrode, and the second transistor chip is electrically coupled to a second one of the bonding pad regions that serves as a second base electrode,    wherein an interconnection region electrically couples the first and second bonding pad regions.    
   
   
       75 . The circuit device of  claim 71  comprising a transistor chip mounted on a surface of a first one of the die pad regions and an IC chip mounted on a surface of a second one of the die pad regions, wherein an interconnection region forms at least part of an electrical path coupling the transistor chip and the IC chip.  
   
   
       76 . The circuit device of  claim 75  comprising a passive circuit element on a surface of a third die pad region.

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