Semiconductor integrated circuit and method for designing same

Abstract

The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17 , which are included in first and second clock circuits 11 and 12 , respectively, are formed by transistors of a unified size. Even if there is manufacturing variability, delay time t 1 of the first clock circuit 11 and delay time t 2 of the second clock circuit 12 are increased or decreased by the same amount of time. Because of this, timing error is not likely to occur in a second flip-flop 15 . A logic cell included in each clock cell may be formed by a transistor having a uniform rectangular-shaped diffusion region.

1 . A semiconductor integrated circuit operating in synchronization with a clock signal, the semiconductor integrated circuit comprising: 
 a plurality of storage cells;    a clock circuit for generating, based on a clock signal supplied thereto, a clock signal to be supplied to each of the storage cells; and    a combinational circuit for generating, based on a value stored in each of the storage cells, a data input signal to be supplied to each of the storage cells,    wherein the clock circuit includes logic cells formed by transistors of a unified size.    
   
   
       2 . The semiconductor integrated circuit according to  claim 1 , wherein the logic cells included in the clock circuit are formed by transistors, each having a uniform rectangular-shaped diffusion region.  
   
   
       3 . A semiconductor integrated circuit design method for designing a semiconductor integrated circuit operating in synchronization with a clock signal, the method comprising the steps of: 
 designing a circuit block having a clock circuit which includes a first clock cell operating under a first operating condition, the circuit block operating under the first operating condition;    replacing the first clock cell included in the clock circuit of the circuit block by a second clock cell which is equivalent to the first clock cell in an input capacitance, a cell-specific delay and a driving capability, the second clock cell operating under a second operating condition; and    designing a semiconductor integrated circuit which includes the circuit block including the second clock cell, the semiconductor integrated circuit operating under the second operating condition.    
   
   
       4 . The semiconductor integrated circuit design method according to  claim 3 , wherein the first and second operating conditions each are related to a threshold voltage.  
   
   
       5 . The semiconductor integrated circuit design method according to  claim 3 , wherein the first are second operating condition each are related to a supply voltage.  
   
   
       6 . A semiconductor integrated circuit design method for designing a semiconductor integrated circuit operating in synchronization with a clock signal, the method comprising the steps of: 
 obtaining the number of toggles in a prescribed service life for each clock signal to be supplied to storage cells included in the semiconductor integrated circuit;    obtaining, based on the obtained number of toggles, a quantity of delay variation at an expiration of the service life for said each clock signal;    obtaining a difference in the quantity of delay variation between a clock signal to be supplied to a first storage cell and a clock signal to be supplied to a second storage cell;    setting the obtained difference, as a design margin for accommodating a delay time variation due to deterioration over time, in timing constraints between the first and second storage cells; and    performing a timing adjustment on a circuit for supplying a signal to the first and second storage cells, in accordance with the timing constraints in which the design margin has been set.    
   
   
       7 . A semiconductor integrated circuit operating in synchronization with a clock signal, the semiconductor integrated circuit comprising: 
 a plurality of circuit blocks;    a clock circuit for generating, based on a clock signal supplied thereto, a clock signal to be supplied to each of the circuit blocks;    a toggle counting circuit for counting the number of toggles of the clock signal to be supplied to each of the circuit blocks; and    a toggle count output circuit for outputting the number of toggles.    
   
   
       8 . A semiconductor integrated circuit operating in synchronization with a clock signal, the semiconductor integrated circuit comprising: 
 a plurality of circuit blocks;    a clock circuit for generating, based on a clock signal supplied thereto, a clock signal to be supplied to each of the circuit blocks;    a toggle counting circuit for counting the number of toggles of the clock signal to be supplied to each of the circuit blocks; and    a toggle adjustment circuit for supplying an adjustment clock signal to a circuit block to which a clock signal whose number of toggles is relatively low is supplied, the adjustment clock signal being different from the clock signal supplied to the clock circuit.    
   
   
       9 . A semiconductor integrated circuit design method for designing a semiconductor integrated circuit operating in synchronization with a clock signal, the method comprising the steps of: 
 designating a type of logic cells which should be present on a clock path; and    determining for each clock path included in the semiconductor integrated circuit whether logic cells present on the clock path are of the designated type.    
   
   
       10 . The semiconductor integrated circuit design method according to  claim 9 , further comprising the steps of: 
 designating, for each type of logic cell which should not be present on a clock path, a type of logic cell which should be present on the clock path and is logically equivalent to the logic cell which should not be present on the clock path; and    replacing, based on a result of the determining step for each clock path included in the semiconductor integrated circuit, a logic cell, which should not be, but is, present on the clock path, with a logic cell, which should be present on the clock path and whose type corresponds to that of the logic cell, which should not be, but is, present on the clock path.    
   
   
       11 . A semiconductor integrated circuit design method for designing a semiconductor integrated circuit operating in synchronization with a clock signal, the method comprising the steps of: 
 obtaining prescribed characteristics of each clock path to storage cells included in the semiconductor integrated circuit;    obtaining a design margin in a prescribed manner based on said prescribed characteristics of a first clock path to a first storage cell and said prescribed characteristics of a second clock path to a second storage cell;    setting the obtained design margin, as a design margin for accommodating a difference between clock paths, in timing constraints between the first and second storage cells; and    performing a timing adjustment on a circuit for supplying a signal to the first and second storage cells, in accordance with the timing constraints in which the obtained design margin has been set.    
   
   
       12 . The semiconductor integrated circuit design method according to  claim 11 , wherein: 
 said prescribed characteristics include the number of stages of logic cells present on the clock path; and    the step of obtaining a design margin obtains the design margin based on a difference in the number of stages of logic cells between the first and second clock paths.    
   
   
       13 . The semiconductor integrated circuit design method according to  claim 11 , wherein: 
 said prescribed characteristics include the number of each type of logic cells present on the clock path; and    the step of obtaining a design margin obtains the design margin based on a difference in the number of each type of logic cells between the first and second clock paths.    
   
   
       14 . The semiconductor integrated circuit design method according to  claim 11 , wherein: 
 said prescribed characteristics include a type of wiring conductors present on the clock path; and    the step of obtaining a design margin obtains the design margin based on a type and a delay time of wiring conductors present on the first clock path and a type and a delay time of wiring conductors present on the second clock path.