Method and apparatus for reducing on-chip memory in vertical video processing
Abstract
A digital image processor includes an input buffer for storing raster-scanned data. A slice-buffer memory is coupled to the input buffer to store a portion of a vertical slice of said raster-scanned data. The vertical slice is processed by a vertical slice processor having an input coupled to the slice-buffer memory. The vertical slice processor reassembles the vertical slices into processed raster-scanned data in an output buffer that is coupled to the output of the vertical slice processor. The digital image processor preferably utilizes multiple sequential processing stages and processes the raster-scanned data along the horizontal axis of the vertical slices.
Claims
exact text as granted — not AI-modified1 . A digital image processor, comprising:
an input buffer storing raster-scanned data; a slice buffer memory coupled to said input buffer to store a portion of a vertical slice of said raster-scanned data; a vertical slice processor having an input coupled to said slice buffer memory; and an output buffer coupled to an output of said vertical slice processor such that said vertical slices are reassembled into processed raster-scanned data in said output buffer.
2 . A digital image processor as recited in claim 1 , wherein the vertical slice processor processes vertical slices of the raster-scanned data along a horizontal axis.
3 . A digital image processor as recited in claim 1 , wherein the vertical slices are comprised of a slice core and at least one pair of wings.
4 (Canceled)
5 A digital image processor as recited in claim 1 , wherein the digital image processor processes the raster-scanned data in multiple sequential processing stages.
6 . A digital image processor as recited in claim 5 , wherein the multiple sequential processing stages individually process along the vertical and horizontal axes.
7 . (Canceled)
8 . (Canceled)
9 . (Canceled)
10 . A method of processing image data, comprising:
buffering a block of raster-scanned data in an input buffer; sequentially retrieving and processing vertical slices of said raster-scanned data from said input buffer to form processed vertical slices; and storing said processed vertical slices in an output buffer to form a processed block of raster-scanned data.
11 . A method of processing image data as recited in claim 10 , including processing vertical slices of the raster-scanned data from the input buffer along a horizontal axis to form horizontally processed raster-scanned data.
12 . A method of processing image data as recited in claim 10 , wherein the vertical slices are comprised of a slice core and at least one pair of wings.
13 . A method of processing image data as recited in claim 12 , wherein the pair of wings each overlap the slice core of horizontally adjacent vertical slices.
14 . A method of processing image data as recited in claim 10 , further including removing at least one of the pair of wings.
15 . (Canceled)
16 . A method of processing image data, comprising:
means for buffering a block of raster-scanned data in an input buffer; means for sequentially retrieving and processing vertical slices of said raster-scanned data from said input buffer to form processed vertical slices; and means for storing said processed vertical slices in an output buffer to form a processed block of raster-scanned data.
17 . A method of processing image data as recited in claim 16 , including means for processing vertical slices of the raster-scanned data from the input buffer along a horizontal axis to form horizontally processed raster-scanned data.
18 . A method of processing image data as recited in claim 16 , wherein the vertical slices are comprised of a slice core and at least one pair of wings.
19 . (Canceled)
20 . A method of processing image data as recited in claim 16 , further including removing at least one of the pair of wings.
21 . A method of processing image data as recited in claim 20 , wherein the width of the processed block of raster-scanned data is equal to the width of the slice core.
22 . A digital image processing system comprising:
a video processor that processes a digital image along a vertical axis by sequencing an image in vertical slices wherein the vertical slices are comprised of a slice core of horizontally adjacent vertical slices and at least one pair of wings, and wherein the at least one pair of wings each overlap the slice core of horizontally adjacent vertical slices; and an external memory, coupled to the video processor, for buffering frame data.
23 . A digital image processing system as recited in claim 22 wherein an video input data is provided as interlaced fields of data in a 720×240 pixel field format.
24 . A digital image processing system as recited in claim 22 wherein the video processor is contained on a chip.Join the waitlist — get patent alerts
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