Suppressing the leakage current in an integrated circuit

Abstract

A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film. Switching circuit 20 is provided between logic circuit 10 and source voltage V dd supply terminal. While in an operating status, 0 V voltage is applied to the gate of transistor MP 0 of switching circuit 20, and bias voltage V B equal to or slightly lower than source voltage V dd is applied to its channel region in order to reduce the threshold voltage of transistor MP 0 and increase its current driving capability. While in a standby status, a voltage equal to source voltage V dd is applied to the gate of transistor MP 0 , a voltage lower than the source voltage is applied to the source, and bulk bias voltage V B equal to or higher than source voltage V dd is applied to the channel region in order to minimize the drain current of transistor MP 0 , so that current path of logic circuit 10 is cut off, and the occurrence of leakage current is suppressed.

1 - 6 . (canceled)  
   
   
       7 . A semiconductor integrated circuit having comprising, 
 multiple functional circuits which perform prescribed processing,    multiple switching circuits which are connected between the source voltage input terminals and the source voltage supply terminals of the functional circuits in correspondence respectively to the multiple functional circuits, and    scan-pass circuits cascade-connected with multiple latching circuits corresponding respectively to the multiple switching circuits; wherein,    voltage signals corresponding to the data stored in the latching circuits are applied to the control terminals of the switching circuits in order to make the switching circuits conductive or non-conductive according to said voltage signals.    
   
   
       8 - 9 . (canceled)