Method and apparatus for pipeline processing a chain of processing instructions

Abstract

Processor instruction pipelines, which split the processing of individual instructions into several sub-stages and thus reduce the complexity of each stage while simultaneously increasing the clock speed, are typical features of RISC architectures. Operands required by the processing are read from a register file. Read-after-write access problems in the pipeline processing can be avoided by using a scoreboard that has an individual entry per address of the register file. Once an instruction enters the pipeline, a flag is set at the address of the destination address of this particular instruction. This flag signals that an instruction inside the pipeline wants to write its result to the respective register address. Hence the result is unavailable as long as the flag is set. It is cleared after the instruction process has successfully written the result into the register file. According to the invention, not only a single flag but the number of the pipeline stage, which currently carries the instruction that wants to write its result to a particular register file address, and the type of the respective instruction is stored in the corresponding scoreboard address for the particular instruction.

1 . Method for pipeline processing a chain of processing instructions, including the step: 
 processing said instructions in a chain of succeeding pipeline stages, wherein partial or intermediate first pipeline processing operands or results are intermediately or permanently stored in a operand/result store, e.g. in a register file, for further access at the appropriate time instant or instants by one or more of said pipeline stages,    and wherein partial or intermediate second pipeline processing operands or results available in one or more of said pipeline stages are accessed by one or more other ones of said pipeline stages at the appropriate time instant or instants without access to said operand/result store,    and wherein a scoreboard is used in which information is stored about the presence or absence of specific ones of said partial or intermediate first pipeline processing operands or results required by subsequent pipeline processing,    and wherein in said scoreboard data are stored and updated about in which one or ones of said pipeline stages a currently required operand or result, or currently required operands or results, is—or are—located available for use in one or more other ones of said pipeline stages,    and in that in said scoreboard, data are stored and updated about the type of instruction that is related to said currently required operand or result, or currently required operands or results,    wherein said one or more other ones of said pipeline stages makes—or make—use of said data about location and said data about instruction type for accessing directly said currently required operand or result, or currently required operands or results, without need to access data stored in said operand/result store.    
   
   
       2 . Method according to  claim 1 , wherein said scoreboard contains an individual incrementer for each address of a register in said operand/result store.  
   
   
       3 . Method according to  claim 2 , wherein the first one of said pipeline stages writes a zero value at the address of a destination register in said scoreboard upon a processing instruction entering said first pipeline stage, and all stage counters related to processing instructions that had previously entered said first pipeline stage are incremented every new cycle if the corresponding pipeline stages are not stalled, such that the current pipeline stage counting number is kept up-to-date, and wherein, upon a processed processing instruction leaving the last pipeline stage of said chain of pipeline stages, said pipeline stage counting number is set to an end value that is no more incremented.  
   
   
       4 . Method according to  claim 1  or  2 , wherein said chain of pipeline stages, except said first and the last pipeline stage, feed partial or intermediate second pipeline processing operands or results available in one or more of said pipeline stages to a common bus from which said partial or intermediate second pipeline processing operands or results can be accessed by one or more other ones of said pipeline stages at the appropriate time instant or instants without access to said operand/result store.  
   
   
       5 . Apparatus for pipeline processing a chain of processing instructions, and including: 
 an operand/result store;    a chain of succeeding pipeline stages, wherein said instructions are processed, whereby partial or intermediate first pipeline processing operands or results are intermediately or permanently stored in said operand/result store, e.g. in a register file, for further access at the appropriate time instant or instants by one or more of said pipeline stages,    and wherein partial or intermediate second pipeline processing operands or results available in one or more of said pipeline stages are accessed by one or more other ones of said pipeline stages at the appropriate time instant or instants without access to said operand/result store;    a scoreboard wherein data are stored and updated about in which one or ones of said pipeline stages a currently required operand or result, or currently required operands or results, is—or are—located available for use in one or more other ones of said pipeline stages, and wherein data are stored and updated about the type of instruction that is related to said currently required operand or result, or currently required operands or results,    and wherein said one or more other ones of said pipeline stages use of said data about location and said data about instruction type for accessing directly said currently required operand or result, or currently required operands or results, without need to access data stored in said operand/result store.    
   
   
       6 . Apparatus according to  claim 5 , wherein said scoreboard contains an individual incrementer for each address of a register in said operand/result store.  
   
   
       7 . Method or apparatus according to  claim 6 , wherein the first one of said pipeline stages writes a zero value at the address of a destination register in said scoreboard upon a processing instruction entering said first pipeline stage, and all stage counters related to processing instructions that had previously entered said first pipeline stage are incremented every new cycle if the corresponding pipeline stages are not stalled, such that the current pipeline stage counting number is kept up-to-date, and wherein, upon a processed processing instruction leaving the last pipeline stage of said chain of pipeline stages, said pipeline stage counting number is set to an end value that is no more incremented.  
   
   
       8 . Method or apparatus according to  claim 5  or  6 , wherein said chain of pipeline stages, except said first and the last pipeline stage, feed partial or intermediate second pipeline processing operands or results available in one or more of said pipeline stages to a common bus from which said partial or intermediate second pipeline processing operands or results can be accessed by one or more other ones of said pipeline stages at the appropriate time instant or instants without access to said operand/result store.