Controlling signal states and leakage current during a sleep mode

Abstract

A circuit includes an input terminal, an output terminal and a latch. The input terminal receives an input signal. The latch is programmable with a value. The latch communicates the input signal to the output terminal in response to the circuit not being in a sleep mode and in response to the circuit being in the sleep mode, furnishes a second signal to the output terminal indicative of the value.

1 - 12 . (canceled)  
   
   
       13 . A level translator comprising: 
 a first circuit responsive to an input signal associated with a first logic one level to generate an output signal associated with a second logic one level different from the first logic one level; and    a second circuit to isolate the first circuit from ground in response to a sleep mode.    
   
   
       14 . The level translator of  claim 13 , wherein the second circuit couples the first circuit to ground in response to the level translator not being in the sleep mode.  
   
   
       15 . The level translator of  claim 13 , wherein the input signal is not at a predefined level during the sleep mode.  
   
   
       16 . The level translator of  claim 13 , wherein the first circuit comprises a least one transistor having a first gate thickness and the second circuit comprises at least one transistor having a second gate thickness substantially greater than the first gate thickness.  
   
   
       17 - 20 . (canceled)  
   
   
       21 . A method comprising: 
 using a level translator to translate logic levels between an input and an output signal; and    selectively blocking current between the level translator and ground to prevent leakage current during a sleep mode.    
   
   
       22 . The method of  claim 21 , wherein the selectively preventing comprises: 
 blocking a current path between the level translator and ground during the sleep mode.    
   
   
       23 . The method of  claim 21 , wherein the act of selectively preventing comprises: 
 coupling the level translator to ground when not in the sleep mode.    
   
   
       24 . The method of  claim 21 , wherein the selectively preventing comprises: 
 using a thicker gate transistor to selectively prevent the current than a transistor used in the level translator.    
   
   
       25 . A level translator comprising: 
 logic transistors;    isolation transistors coupled to limit voltage levels across the logic transistors; and    pullup transistors coupled between the isolation transistors and a voltage supply.    
   
   
       26 . The level translator of  claim 25 , further comprising: 
 an inverter to generate a control signal for at least one of the logic transistors, wherein the inverter is powered by another lower voltage supply capable of being turned off prior to the turning off of the first voltage supply.    
   
   
       27 . The level translator of  claim 25 , wherein the logic transistors operate from a second lower voltage supply capable of being turned off prior to the turning off of the first voltage supply.  
   
   
       28 . The level translator of  claim 25 , further comprising: 
 a control transistor to selectively couple the logic transistors to ground to selectively enable operation of the logic transistors.    
   
   
       29 . A level translator comprising: 
 logic transistors;    a control transistor to selectively couple the logic transistors to ground to selectively enable operation of the logic transistors;    an inverter to generate a control signal for at least one of the logic transistors, wherein the inverter is powered by a first voltage supply capable of being turned off prior to the turning off of a second higher voltage supply; and    pullup transistors coupled between the logic transistors and the second higher voltage supply.    
   
   
       30 . The level translator of  claim 29 , wherein operation of the control transistor is regulated in response to a signal indicative of a sleep mode.