US2005091618A1PendingUtilityA1

Method and apparatus for decomposing and verifying configurable hardware

37
Priority: Nov 12, 2002Filed: Oct 29, 2004Published: Apr 28, 2005
Est. expiryNov 12, 2022(expired)· nominal 20-yr term from priority
G01R 31/318314G06F 30/33G06F 11/26Y02E30/30G06F 15/00G06F 11/30G21C 17/00
37
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Claims

Abstract

The present invention includes a method and apparatus for decomposing and verifying configurable hardware. In one embodiment, the method includes automatically decomposing a hardware system into a set of one or more units, creating a testbench for each of the set of units, and verifying each of the set of units before verifying the hardware system design.

Claims

exact text as granted — not AI-modified
1 . A computer implemented method comprising: 
 automatically decomposing a hardware system into a set of one or more units;    creating a testbench for each of the set of units; and    verifying each of the set of units before verifying the hardware system.    
     
     
         2 . The computer implemented method of  claim 1 , wherein said set of units is defined in a configurable hardware library, and wherein said system is specified in a configuration data storage unit.  
     
     
         3 . The computer implemented method of  claim 2 , wherein said configuration data is represented in a hierarchical language and wherein said configurable hardware library is represented in hardware design language (HDL).  
     
     
         4 . The computer implemented method of  claim 1 , wherein said testbenches include models attached to each unit connection, wherein said models send data to and receive data from said unit according to parameters of the unit.  
     
     
         5 . A computer implemented method comprising: 
 automatically decomposing a set of one or more units at a first level of a configurable hardware system design hierarchy, into a set of one or more units of a lowest level of the hardware system design hierarchy, wherein the configurable hardware system design hierarchy includes a set of one or more hierarchy levels; and    individually verifying units of each hierarchy level of the hardware system design hierarchy successively from the lowest level to the first level with test benches dynamically built for each unit of each successive level.    
     
     
         6 . The computer implemented method of  claim 5 , wherein said automatically decomposing is based on configuration data and the contents of a configurable hardware library.  
     
     
         7 . The computer implemented method of  claim 6 , wherein said configuration data specifies parameters for the units of each of the set of configurable hardware system design levels.  
     
     
         8 . The computer implemented method of  claim 6 , wherein said configurable hardware library defines the units of each of the set of hierarchy levels.  
     
     
         9 . A computer implemented method comprising: 
 mapping a set of configuration data onto a corresponding configurable unit definition selected from a configurable hardware library to generate a set of one or more configurable hardware units; dynamically generating a test bench for each of the set of configurable hardware units based on the configuration data;    verifying each of the set of configurable hardware units with their corresponding test bench; integrating the verified set of configurable hardware units into a configurable hardware system; and verifying the configurable hardware system.    
     
     
         10 . The computer implemented method of  claim 9  further comprising: 
 generating tests to be run on said testbenches;    generating scripts for executing said tests; and    generating inputs to an analysis tool.    
     
     
         11 . The computer implemented method of  claim 9 , wherein said corresponding configurable unit definition is represented in hardware design language (HDL).  
     
     
         12 . The computer implemented method of  claim 9 , wherein said configuration data is represented in tool control language (TCL), and wherein said configuration data defines parameters for each of the set of configurable hardware units.  
     
     
         13 . The computer implemented method of  claim 9  wherein said testbenches include models connected to each communication path of the unit.  
     
     
         14 - 39 . (canceled)

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