Device packages with low stress assembly process

Abstract

A microelectromechanical device package and a low-stress inducing method for packaging a microelectromechanical device are disclosed in this invention. The microelectromechanical device is accommodated within a cavity comprised by a first package substrate and a second substrate, wherein a third substrate is disposed between and bonded to both the microelectromechanical device lower semiconductor substrate and the package bottom substrate. The first and second package substrates are then bonded so as to package the microelectromechanical device inside.

1 . A packaged microelectromechanical device, comprising: 
 a microelectromechanical array device that comprises a semiconductor substrate;    a package for the microelectromechanical array device, the package comprising a packaging substrate;    an insert substrate that is disposed between the semiconductor substrate and the package substrate; and    wherein the insert substrate has a CTE value that is the sane as a CTE value of the semiconductor substrate or between the value of the semiconductor substrate and a CTE value of the package substrate.    
   
   
       2 . The device of  claim 1 , wherein the semiconductor substrate is silicon.  
   
   
       3 . The device of  claim 2 , wherein the microelectromechanical array comprises a light transmissive substrate bonded to the semiconductor substrate.  
   
   
       4 . The device of  claim 3 , wherein the light transmissive substrate is glass or quartz.  
   
   
       5 . The device of  claim 3 , wherein the microelectromechanical array comprises a plurality of micromirrors formed on the light transmissive substrate.  
   
   
       6 . The device of  claim 5 , wherein the semiconductor substrate comprises an array of electrodes for electrostatically attracting the micromirrors.  
   
   
       7 . The device of  claim 6 , wherein at least 500,000 micromirrors are disposed on the light transmissive substrate.  
   
   
       8 . The device of  claim 1 , wherein the microelectromechanical array are formed directly on the semiconductor substrate.  
   
   
       9 . The device of  claim 8 , wherein the semiconductor substrate comprises an array of electrodes.  
   
   
       10 . The device of  claim 1 , wherein the package laminate substrate layers are ceramic.  
   
   
       11 . The device of  claim 1 , wherein the package laminate substrate layers are glass.  
   
   
       12 . The device of  claim 1 , wherein the plurality of the package laminate substrate layers form a cavity in which the micromirror array device is located.  
   
   
       13 . The device of  claim 1 , wherein the package laminate is a flat plate.  
   
   
       14 . The device of  claim 1 , wherein the package laminate comprises an inlay glass that is transmissive to visible light.  
   
   
       15 . The device of  claim 1 , wherein the third substrate has a CTE that is the same as the semiconductor substrate Or between the CTE values of the semiconductor substrate and the package laminate bottom substrate.  
   
   
       16 . The device of  claim 15 , wherein the CTE ranges from 3×10 4  to 7×10 41 .  
   
   
       17 . The device of  claim 16 , wherein the third substrate is silicon.  
   
   
       18 . The device of  claim 17 , wherein the third substrate is bonded to the semiconductor substrate with adhesives.  
   
   
       19 . The device of  claim 18 , wherein the adhesives are organic adhesives.  
   
   
       20 . The device of  claim 1 , wherein the insert substrate is bonded to the semiconductor substrate with an adhesive.  
   
   
       21 . The device of  claim 1 , wherein the third substrate further comprises a discontinuous layer or plurality of layers.  
   
   
       22 . (canceled).  
   
   
       23 . The device of  claim 1 , wherein the package laminate further comprises: 
 a first substrate having a heater along a periphery of the top surface of the first substrate and underneath said top surface;    a second substrate above the first substrate; and    a first sealing medium layer bonding the first substrate and the second substrate together.    
   
   
       24 . The device of  claim 24 , wherein the first sealing medium layer further comprises a glass frit or solderable metallic material that bonds the first and second substrates together.  
   
   
       25 . The device of  claim 24 , wherein the first substrate is a multilayered structure that comprises a plurality of substrate layers.  
   
   
       26 . The device of  claim 24 , wherein the heater has a zigzag shape.  
   
   
       27 . The device of  claim 24 , wherein the heater comprises a metallic material.  
   
   
       28 . The device of  claim 24 , wherein the metallic material of the heater is formed by sputtering.  
   
   
       29 . The device of  claim 24 , wherein the first substrate is ceramic.  
   
   
       30 . The device of  claim 24 , wherein the second substrate is glass that is transparent to visible light.  
   
   
       31 . The device of  claim 24 , wherein at least one surface of the second glass substrate is deposited thereon an anti-reflection layer for enhancing transmission of visible light through the glass substrate.  
   
   
       32 . The device of  claim 24 , wherein the second substrate further comprises: another heater along a periphery of a surface of the second substrate and underneath said surface of the second substrate.  
   
   
       33 . The device of  claim 24 , wherein the first sealing medium layer is a multilayered structure that further comprises a plurality of solderable metallization layers for metalizing the surface of the first substrate.  
   
   
       34 . The device of  claim 24 , wherein the first sealing medium layer is a solderable metallization layer for metalizing the surface of the first substrate.  
   
   
       35 . A method of packaging a microelectromechanical array device having a semiconductor substrate to a package, the method comprising: 
 selecting an insert substrate whose CTE value is the same as the CTE value of the semiconductor substrate or between the CTE value of the semiconductor substrate and a CTE value of a package substrate of the package:    attaching the semiconductor substrate to the insert substrate using an adhesive so as to form an assembly; and    attaching the insert substrate of said assembly to the package substrate using an adhesive.    
   
   
       36 . The method of  claim 35 , wherein the adhesive for attaching the semiconductor substrate to the insert substrate is deposited in an even layer covering at least 80% of said substrate surface.  
   
   
       37 . The method of  claim 36 , wherein the adhesive for attaching the insert substrate of the assembly to the package substrate is deposited in an even layer covering at least 80% of said substrate surface.  
   
   
       38 . (canceled)  
   
   
       39 . The method of  claim 36 , wherein the adhesive for attaching the microelectromechanical array with semiconductor substrate to another substrate is deposited on the middle of said substrate covering at least 33% of its surface.  
   
   
       40 . The method of  claim 41 , wherein the adhesive for attaching the assembly to the package laminate bottom substrate is deposited on the middle of said substrate covering at least 33% of its surface.  
   
   
       41 . The method of  claim 36 , wherein the substrate with similar mechanical properties forms a discontinuous layer or plurality of layers.  
   
   
       42 . The method of  claim 36 , further comprising: 
 depositing an anti-stiction material within the cavity defined by the package laminate substrate.    
   
   
       43 . The device of  claim 1 , wherein the package substrate is ceramic.  
   
   
       44 . A packaged microelectromechanical device, comprising: 
 a microelectromechanical array device that comprises a semiconductor substrate;    a package substrate having a cavity in which the microelectromechanical array device is disposed; and    an insert substrate that is disposed between the semiconductor substrate and the package substrate.    
   
   
       45 . The device of  claim 44 , wherein the package substrate is ceramic.  
   
   
       46 . The device of  claim 44 , further comprising: 
 an array of electrodes and circuitry on the semiconductor substrate; and    an array of micromirrors disposed proximate to the electrodes such that the micromirrors can be electrostatically actuated by the electrodes.    
   
   
       47 . The device of  claim 46 , wherein the micromirrors are formed on the semiconductor substrate.  
   
   
       48 . The device of  claim 46 , wherein the micromirrors are formed on a light transmissive substrate that is bonded to the semiconductor substrate.  
   
   
       49 . A packaged microelectromechanical device, comprising: 
 a microelectromechanical array device that comprises a semiconductor substrate;    a ceramic package substrate having a supporting surface; and    an insert substrate that is disposed between the semiconductor substrate and the supporting surface of the ceramic package substrate.    
   
   
       50 . The device of  claim 49 , wherein the supporting surface is within a cavity of the ceramic package substrate.  
   
   
       51 . The device of  claim 50 , further comprising: 
 an array of electrodes and circuitry on the semiconductor substrate; and    an array of micromirrors disposed proximate to the electrodes such that the micromirrors can be electrostatically actuated by the electrodes.    
   
   
       52 . The device of  claim 51 , wherein the micromirrors are formed on the semiconductor substrate.  
   
   
       53 . The device of  claim 51 , wherein the micromirrors are formed on a light transmissive substrate that is bonded to the semiconductor substrate.  
   
   
       54 . The device of  claim 1 , wherein the insert substrate comprises a plurality of substrates.  
   
   
       55 . A method of packaging a microelectromechanical array device having a semiconductor substrate to a package, the method comprising: 
 selecting an insert substrate whose CTE value is the same as the CTE value of the semiconductor substrate or between the CTE value of the semiconductor substrate and a CTE value of a package substrate of the package;    attaching the package substrate to the insert substrate using an adhesive so as to form an assembly; and    attaching the insert substrate of said assembly to the semiconductor substrate using an adhesive.