Non-volatile memory and method of manufacturing floating gate

Abstract

A method of manufacturing a floating gate is provided. The method includes the steps of forming a tunneling layer on a substrate, and forming a film layer containing a semiconductor component on the tunneling layer. The film layer consists of a semiconductor film or nano-dots.

1 . A method of manufacturing a floating gate, comprising: 
 forming a tunneling layer on a substrate; and    forming a film with a semiconductor component, on the tunneling layer,    wherein the film with a semiconductor component consists of nano-dots or a thin film.    
     
     
         2 . The method according to  claim 1 , wherein the semiconductor component in the film is selected from the group consisting of Group II elements, Group III elements, Group IV elements, Group V elements, Group VI elements, and compounds thereof.  
     
     
         3 . The method according to  claim 1 , wherein the semiconductor component in the film is selected form the group consisting of germanium (Ge), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), cadmium sulfide (CdS), zinc sulfide (ZnS), and zinc selenide (ZnSe).  
     
     
         4 . The method according to  claim 1 , wherein the film with a semiconductor component is a semiconductor oxide layer consisting of nano-dots or a thin film.  
     
     
         5 . The method according to  claim 4 , wherein the semiconductor oxide layer is formed via physical vapor deposition or chemical vapor deposition.  
     
     
         6 . The method according to  claim 4 , wherein the process of forming the semiconductor oxide layer comprises: 
 forming a semiconductor silicide layer on the tunneling layer;    performing a first oxidation process to oxide the semiconductor silicide layer so that the semiconductor component in the semiconductor silicide layer is educed and settled on the tunneling layer to form a plurality of semiconductor nano-dots; and    performing a second oxidation process to oxide the semiconductor nano-dots.    
     
     
         7 . The method according to  claim 6 , wherein the first oxidation step is of dry oxidation or wet oxidation.  
     
     
         8 . The method according to  claim 6 , the second oxidation step is of wet oxidation.  
     
     
         9 . The method according to  claim 6 , further comprising, between the first and the second oxidation processes, a thermal process to reduce the partially oxidized semiconductor component so that the semiconductor nano-dots are educed.  
     
     
         10 . The method according to  claim 4 , further comprising formation of a dielectric layer at the same time when the semiconductor oxide layer is formed.  
     
     
         11 . The method according to  claim 10 , wherein the semiconductor oxide layer is formed via a process comprising the steps of: 
 forming a semiconductor layer on the tunneling layer, the semiconductor layer consisting of nano-dots or a thin film;    forming a silicon layer on the semiconductor layer; and    performing an oxidation process to oxidize the semiconductor layer and the silicon layer.    
     
     
         12 . The method according to  claim 4 , wherein the semiconductor oxide layer is formed via a process comprising the steps of: 
 forming a semiconductor layer on the tunneling layer, the semiconductor layer consisting of nano-dots or a thin film;    forming a dielectric layer on the semiconductor layer; and    performing an oxidation annealing process to oxidize the semiconductor layer.    
     
     
         13 . The method according to  claim 1 , wherein the film with a semiconductor component consists of nano-dots or a thin film.  
     
     
         14 . The method according to  claim 13 , wherein the nano-dots are formed via a process comprising the steps of: 
 forming a semiconductor silicide layer on the tunneling layer; and    oxidizing the semiconductor silicide layer such that the semiconductor component of the semiconductor silicide layer is educed and settled on the tunneling layer to form the semiconductor nano-dots.    
     
     
         15 . The method according to  claim 14 , wherein the semiconductor silicide layer on the tunneling layer is formed via physical vapor deposition or chemical vapor deposition.  
     
     
         16 . The method according to  claim 14 , further comprising the step of: 
 performing a thermal process to reduce the partially oxidized semiconductor component so that the semiconductor nano-dots are educed.    
     
     
         17 . A non-volatile memory comprising: 
 a tunneling layer disposed on a substrate;    a dielectric layer disposed over the tunneling layer;    a floating gate disposed between the tunneling layer and the dielectric layer,    wherein the floating gate contains a semiconductor component consisting of nano-dots or a thin film;    a control gate disposed on the dielectric layer; and    a source region and a drain region, disposed respectively on two sides of the control gate in the substrate.    
     
     
         18 . The non-volatile memory according to  claim 17 , wherein the semiconductor component contained in the floating gate is selected from the group consisting of Group II elements, Group III elements, Group IV elements, Group V elements, Group VI elements, and compounds thereof.  
     
     
         19 . The non-volatile memory according to  claim 17 , wherein the semiconductor component contained in the floating gate is selected from the group consisting of germanium (Ge), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), cadmium sulfide (CdS), zinc sulfide (ZnS), and zinc selenide (ZnSe).  
     
     
         20 . The non-volatile memory according to  claim 17 , wherein the floating gate consists of semiconductor oxide film, semiconductor oxide nano-dots, or semiconductor nano-dots.