Radiation-hardened transistor fabricated by modified CMOS process

Abstract

An NMOS field effect transistor ( 1 ) is made radiation hard by a pair of guard band implants ( 115 ) of limited horizontal extent, extending between the source ( 30 A) and drain ( 30 B) along the edge of the transistor body, and extending only to a limited extent into the field insulator and into the interior of the transistor, leaving an unimplanted area in the center of the body that retains the transistor design threshold voltage.

1 . A method of forming a field effect transistor, comprising: preparing a semiconductor substrate; 
 defining an active area containing a source area that will contain a source and a drain area that will contain a drain, said source drain areas being separated by a body area;    forming isolating dielectric on at least two sides of said active area, said isolating dielectric abutting said body area and at least a portion of said source area and said drain area;    doping two guard bands on opposite sides of said active area with a leakage-suppressing dopant, said two guard bands extending inward from said edge of said active area into said body by a dopant body distance and separated by a body area; and    forming a gate insulator, a gate and a source and drain of said transistor.    
   
   
       2 . A method according to  claim 1 , in which said step of doping is performed after said step of forming said isolating dielectric, whereby said two guard bands extend outward from an edge of said active area into said isolating dielectric by a dopant field distance.  
   
   
       3 . A method according to  claim 1 , in which said step of doping is performed before said step of forming said isolating dielectric.  
   
   
       4 . A method according to  claim 1 , in which said two guard bands extend horizontally along a first axis perpendicular to said gate of said transistor from a starting point within said source of said transistor to an end point within said drain of said transistor.  
   
   
       5 . A method according to  claim 1 , in which said guard bands extend vertically below a bottom surface of said source and drain by a vertical tolerance distance.  
   
   
       6 . A method according to  claim 4 , in which said guard bands extend vertically below a bottom surface of said source and drain by a vertical tolerance distance.  
   
   
       7 . A method according to  claim 2 , in which said two guard bands extend horizontally along a first axis perpendicular to said gate of said transistor from a starting point within said source of said transistor to an end point within said drain of said transistor.  
   
   
       8 . A method according to  claim 2 , in which said guard bands extend vertically below a bottom surface of said source and drain by a vertical tolerance distance.  
   
   
       9 . A method according to  claim 7 , in which said guard bands extend vertically below a bottom surface of said source and drain by a vertical tolerance distance.  
   
   
       10 . A method according to  claim 3 , in which said two guard bands extend horizontally along a first axis perpendicular to said gate of said transistor from a starting point within said source of said transistor to an end point within said drain of said transistor.  
   
   
       11 . A method according to  claim 3 , in which said guard bands extend vertically below a bottom surface of said source and drain by a vertical tolerance distance.  
   
   
       12 . A method according to  claim 11 , in which said guard bands extend vertically below a bottom surface of said source and drain by a vertical tolerance distance.  
   
   
       13 . A method of forming a field effect transistor, comprising: 
 preparing a semiconductor substrate;    defining an active area containing a source area that will contain a source and a drain area that will contain a drain, said source and drain areas being separated by a body area;    forming isolating dielectric on at least two sides of said active area, said isolating dielectric abutting said body area and at least a portion of said source area and said drain area;    implanting two guard bands at least on opposite sides of said active area with a leakage-suppressing dopant, extending inward from said edge of said active area into said body by an implant body distance and separated by an unimplanted area; and    forming a gate insulator, a gate and a source and drain of said transistor.    
   
   
       14 . A method according to  claim 13 , in which said step of implanting is performed after said step of forming said isolating dielectric, whereby said two guard bands extend outward from an edge of said active area into said isolating dielectric by an implant field distance.  
   
   
       15 . A method according to  claim 13 , in which said step of implanting is performed before said step of forming said isolating dielectric.  
   
   
       16 . A method according to  claim 13 , in which said two guard bands extend horizontally along a first axis perpendicular to said gate of said transistor from a starting point within said source of said transistor to an end point within said drain of said transistor.  
   
   
       17 . A method according to  claim 13 , in which said implant extends vertically below a bottom surface of said source and drain by a vertical tolerance distance.  
   
   
       18 . A method according to  claim 16 , in which said implant extends vertically below a bottom surface of said source and drain by a vertical tolerance distance.  
   
   
       19 . A method according to  claim 14 , in which said two guard bands extend horizontally along a first axis perpendicular to said gate of said transistor from a starting point within said source of said transistor to an end point within said drain of said transistor.  
   
   
       20 . A method according to  claim 14 , in which said implant extends vertically below a bottom surface of said source and drain by a vertical tolerance distance.  
   
   
       21 . A method according to  claim 19 , in which said implant extends vertically below a bottom surface of said source and drain by a vertical tolerance distance.  
   
   
       22 . A method according to  claim 15 , in which said two guard bands extend horizontally along a first axis perpendicular to said gate of said transistor from a starting point within said source of said transistor to an end point within said drain of said transistor.  
   
   
       23 . A method according to  claim 15 , in which said implant extends vertically below a bottom surface of said source and drain by a vertical tolerance distance.  
   
   
       24 . A method according to  claim 22 , in which said implant extends vertically below a bottom surface of said source and drain by a vertical tolerance distance.  
   
   
       25 .- 40 . (canceled)