Wafer level package having a side package

Abstract

A method of manufacturing a wafer level package includes forming a semiconductor wafer including semiconductor chips, and forming a package body on the sides of each semiconductor chip. The package body is formed by forming a space between each semiconductor chip and potting a package material in the space, which can be a mold resin. The wafer is then separated into separate semiconductor chips by cutting through the package body.

1 . A wafer level package comprising: 
 a semiconductor chip, wherein the semiconductor chip includes a plurality of electrode pads on an active surface; and    a package body formed on the sides of the semiconductor chip.    
   
   
       2 . The wafer level package of  claim 1 , further comprising: 
 an insulating layer formed on the active surface, wherein the plurality of electrode pads are exposed;    a metal wiring layer formed on the insulating layer and electrically connected with the plurality of electrode pads;    an insulating layer formed on the metal wiring layer including an opening to the metal wiring layer.    
   
   
       3 . The wafer level package of  claim 2 , wherein the insulating layer formed on the active surface comprises: 
 a passivation layer formed on the active surface; and    a first insulating layer formed on the passivation layer.    
   
   
       4 . The wafer level package of  claim 2 , wherein the metal wiring layer comprises: 
 a plurality of metal wiring layers.    
   
   
       5 . The wafer level package of  claim 2 , wherein the metal wiring layer is a Cu metal layer.  
   
   
       6 . The wafer level package of  claim 2 , wherein the height of the package body extends from a lower surface of the semiconductor chip to the top of the insulating layer formed on the metal wiring layer.  
   
   
       7 . The wafer level package of  claim 2 , further comprising: 
 a connection formed on the metal wiring layer through the opening.    
   
   
       8 . The wafer level package of  claim 7 , wherein the connection is a solder ball connection.  
   
   
       9 . The wafer level package of  claim 1 , wherein the package body is contiguous about the semiconductor chip.  
   
   
       10 . The wafer level package of  claim 1 , wherein the package body includes an epoxy molded resin.  
   
   
       11 . A wafer level package comprising: 
 a wafer including a plurality of semiconductor chips;    a package body formed on all sides of each semiconductor chip of the plurality of semiconductor chips.