Signal processing method and apparatus and disk device using the method and apparatus

Abstract

A signal processing circuit having a data sync signal detector and a disk device. Input data read from a magnetic disk is input to a data discriminator. A data discrimination output constituting a code bit output discriminated by the data discriminator is input to a post-coder the output of which is input to a decoder and a (1+D) processing unit. The processed output of the processing unit is input to an error detection/correction unit and separated into bit strings of odd numbered bits and even numbered bits, divided into groups. An error detection/correction output is input to a data sync signal detector, and matched against a sync pattern. When the number of coincident groups is greater than a threshold value, a sync signal is output and upon detection causes the decoder to demodulate the data.

1 . A data processing device comprising: 
 a discriminator for discriminating input data and outputting discriminated data;    a decoder for decoding data based on the discriminated data and outputting decoded data;    a (1+D) processor for processing data based on the discriminated data and outputting (1+D) processed data;    a detecting/correcting processor for detecting/correcting error of the (1+D) processed data and outputting detected/corrected processed data; and    a data sync signal detector for detecting a data sync signal of the detected/corrected processed data in comparison with predetermined sync pattern and outputting a detected data sync signal to the decoder,    wherein the decoder decodes the data when receiving the detected data sync signal.    
   
   
       2 . The data processing device according to  claim 1 , wherein the predetermined sync pattern includes two 9-bit patterns.  
   
   
       3 . The data processing device according to  claim 2 , wherein each of the 9-bit patterns is configured with a 4-bit code and a 5-bit Cyclic Redundancy Check Code corresponding to the 4-bit code.  
   
   
       4 . The data processing device according to  claim 2 , wherein a remainder of each of the 9-bit patterns divided by a generator polynomial of degree  5  is zero.