Method of forming a pattern in a semiconductor device and method of forming a gate using the same

Abstract

A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

1 . A method of forming a pattern of a semiconductor device, comprising: 
 providing a semiconductor substrate on which an object layer to be patterned is formed, the substrate being divided into a cell region and a peripheral region;    forming a buffer layer on the object layer;    partially etching the buffer layer by a photolithography process such that the buffer layer in the cell region of the substrate is formed into a buffer pattern, and the buffer layer in the peripheral region of the substrate is removed;    forming a hard mask layer on the buffer pattern in the cell region and the object layer in the peripheral region;    selectively etching the hard mask layer only in the cell region of the substrate anisotropically, so that a spacer is formed along a sidewall of the buffer pattern in the cell region, and the hard mask layer still remains on the object layer in the peripheral region of the substrate;    removing the buffer pattern from the object layer, so that only the spacer remains on the object layer along a first direction;    at least partially removing the spacer in a second direction different from the first direction and the hard mask layer, so that the spacer is separated along the second direction, thereby forming a cell hard mask pattern in the cell region and a peripheral hard mask pattern is formed in the peripheral region; and    etching the object layer using the cell hard mask pattern and the peripheral hard mask pattern as an etching mask.    
     
     
         2 . The method of  claim 1 , wherein the buffer layer comprises a material having an etching selectivity with respect to the hard mask layer.  
     
     
         3 . The method of  claim 1 , wherein the hard mask layer comprises a material having an etching selectivity with respect to both the object layer and the buffer layer.  
     
     
         4 . The method of  claim 1 , the buffer layer includes at least one of a silicon oxide layer and a polysilicon layer.  
     
     
         5 . The method of  claim 1 , further comprising forming a separation layer between the object layer and the buffer layer for separating the object layer from the buffer layer, the separation layer comprising a material having a high etching selectivity with respect to the object layer when the object layer comprises the same material as the buffer layer.  
     
     
         6 . The method of  claim 1 , wherein the hard mask layer comprises at least one of a silicon oxynitride layer and a silicon oxide layer.  
     
     
         7 . The method of  claim 1 , wherein the object layer includes a gate electrode layer, a silicon substrate in a field region or a metal layer for forming a metal wiring.  
     
     
         8 . The method of  claim 1 , wherein a width of the spacer is less than a critical dimension (CD) of a photolithography process.  
     
     
         9 . The method of  claim 1 , wherein a line width of the peripheral hard mask pattern is greater than that of the cell hard mask pattern.  
     
     
         10 . A method of forming a pattern of a semiconductor device, comprising: 
 providing a semiconductor substrate on which an object layer to be patterned is formed, the substrate being divided into a cell region and a peripheral region;    forming a buffer layer on the object layer;    at least partially etching the buffer layer from the object layer by a photolithography process such that the buffer layer in the cell region of the substrate is formed into a buffer pattern, and the buffer layer in the peripheral region of the substrate is removed;    forming a spacer along a sidewall of the buffer pattern;    removing the buffer pattern from the object layer, so that only the spacer remains on the object layer along a first direction;    forming a hard mask layer on the object layer including the spacer extending along the first direction;    at least partially removing the hard mask layer and the spacer in a second direction different from the first direction in the cell region of the substrate, so that the spacer and the hard mask layer on the spacer are separated from each other along the second direction in the cell region;    at least partially removing the hard mask layer such that the hard mask layer on the spacer is removed in the cell region of the substrate and the hard mask layer on the object layer is at least partially removed in the peripheral region of the substrate, thereby forming a cell hard mask pattern in the cell region of the substrate and a peripheral hard mask pattern in the peripheral region of the substrate; and    at least partially etching the object layer using the cell hard mask pattern and the peripheral hard mask pattern as an etching mask.    
     
     
         11 . The method of  claim 10 , wherein the buffer layer comprises a material having a high etching selectivity with respect to the hard mask layer.  
     
     
         12 . The method of  claim 10 , further comprising, in case that the object layer comprises the same material as the buffer layer, forming a separation layer between the object layer and the buffer layer for separating the object layer from the buffer layer, the separation layer comprising a material having a high etching selectivity with respect to the object layer.  
     
     
         13 . The method of  claim 10 , wherein the spacer and the hard mask layer comprise a material having a high etching selectivity with respect to the object layer and the buffer layer.  
     
     
         14 . The method of  claim 10 , wherein the hard mask layer is the same material as the spacer.  
     
     
         15 . The method of  claim 10 , wherein the hard mask layer comprises at least one of a silicon oxynitride layer and a silicon oxide layer.  
     
     
         16 . The method of  claim 10 , wherein the object layer includes at least one of a gate electrode layer, a silicon substrate in a field region and a metal layer for forming a metal wiring.  
     
     
         17 . A method of forming a gate in a semiconductor device, comprising: 
 forming a gate oxide layer and a gate electrode layer on a substrate, the substrate being divided into a cell region and a peripheral region;    forming a buffer layer on the gate electrode layer;    at least partially etching the buffer layer from the gate electrode layer by a photolithography process such that the buffer layer in the cell region of the substrate is formed into a buffer pattern, and the buffer layer in the peripheral region of the substrate is removed;    forming a hard mask layer on the buffer pattern in the cell region of the substrate and the gate electrode layer in the peripheral region of the substrate;    selectively etching the hard mask layer only in the cell region of the substrate anisotropically, so that a spacer is formed along a sidewall of the buffer pattern in the cell region, and the hard mask layer still remains on the gate electrode layer in the peripheral region of the substrate;    removing the buffer pattern from the gate electrode layer, so that only the spacer remains on the gate electrode layer along a first direction;    at least partially removing the spacer in a second direction different from the first direction and the hard mask layer, so that the spacer is separated the second direction, thereby forming a cell hard mask pattern in the cell region and a peripheral hard mask pattern in the peripheral region; and    at least partially etching the gate electrode layer using the cell hard mask pattern and the peripheral hard mask pattern as an etching mask.    
     
     
         18 . The method of  claim 17 , wherein the gate electrode layer comprises polysilicon.  
     
     
         19 . The method of  claim 18 , wherein the buffer layer includes at least one of a silicon oixde layer and a polysiliocn layer.  
     
     
         20 . The method of  claim 19 , further comprising, in case that the buffer layer includes the polysilicon layer, forming a separation layer between the gate electrode layer and the buffer layer for separating the gate electrode layer from the buffer layer, the separation layer comprising a material having a high etching selectivity with respect to polysilicon.  
     
     
         21 . The method of  claim 17 , wherein the hard mask layer comprises at least one of a silicon oxynitride layer and a silicon oxide layer.  
     
     
         22 . A method of forming a gate in a semiconductor device, comprising: 
 forming a gate oxide layer and a gate conductive layer on a substrate that is divided into a cell region and a peripheral region;    forming a buffer layer on the gate conductive layer;    at least partially etching the buffer layer from the gate conductive layer by a photolithography process such that the buffer layer in the cell region of the substrate is formed into a buffer pattern, and the buffer layer in the peripheral region of the substrate is removed;    forming a spacer along a sidewall of the buffer pattern;    removing the buffer pattern from the gate conductive layer, so that only the spacer remains on the gate conductive layer along a first direction;    forming a hard mask layer on the gate conductive layer including the spacer extending along the first direction;    at least partially etching the hard mask layer and the spacer in a second direction different from the first direction in the cell region of the substrate, so that the spacer and the hard mask layer on the spacer are separated from each other along the second direction in the cell region;    at least partially etching the hard mask layer such that the hard mask layer on the spacer is removed in the cell region of the substrate and the hard mask layer on the gate conductive layer is at least partially removed in the peripheral region of the substrate, thereby forming a cell hard mask pattern in the cell region of the substrate and a peripheral hard mask pattern in the peripheral region of the substrate; and    at least partially etching the gate conductive layer using the cell hard mask pattern and the peripheral hard mask pattern as an etching mask.    
     
     
         23 . The method of  claim 22 , wherein the gate electrode layer comprises polysilicon.  
     
     
         24 . The method of  claim 23 , wherein the buffer layer includes at least one of a silicon oxide layer and a polysilicon layer.  
     
     
         25 . The method of  claim 24 , further comprising, in case that the buffer layer comprises polysilicon, forming a separation layer between the gate conductive layer and the buffer layer for separating the gate conductive layer from the buffer layer, the separation layer comprising a material having an etching selectivity with respect to the polysilicon.  
     
     
         26 . The method of  claim 22 , wherein the hard mask layer includes at least one of a silicon oxynitride layer and a silicon oxide layer.