Bandwidth-adaptive, hybrid, cache-coherence protocol

Abstract

A cache coordination mechanism for a multiprocessor, shared-memory computer switches between a snooping mechanism where an individual processor unit broadcasts or multicasts cache coherence messages to each other node on the system and a directory system where the individual processor unit transmits the cache control message to a directory which then identifies potential candidates to receive that message. The switching is according to the activity on the communication network used by the cache coherence messages. When network activity is high, a directory protocol is used to conserve bandwidth but when network activity is low, a snooping system is used to provide faster response.

1 . A method of coordinating at least two processor units, each having a processor and cache memory, and communicating cache coherence messages with each other and a directory over a network, the method comprising the steps of: 
 (a) multicasting from a given processor unit, a cache coherence message to a selected set of other processor units, based on a prediction as to which other processor units have cache memories loaded with relevant data;    (b) using the directory to detect insufficiency in the selected set of other processor units to which transmission of the cache coherence message is made; and    (c) upon a detected insufficiency, causing the directory to retry the multicast transmission of the cache coherence message.    
   
   
       2 . The method recited in  claim 1  including the step of 
 (d) upon repeated insufficiency in step (c), broadcasting the given cache coherence message to all processor units.    
   
   
       3 . The method recited in  claim 1  wherein the repeated insufficiency is a predetermined number less than ten.  
   
   
       4 . The method recited in  claim 1  wherein the directory sends the retry multicast transmissions to processor units likely to have the relevant data based on a monitoring of cache coherence messages from processor units.  
   
   
       5 . The method of  claim 1  wherein the directory appends a retry number to retires of the cache coherence message.  
   
   
       6 . The method of  claim 5  wherein the processor units responding to the retries appends the retry number to the responses to the retried cache coherence message.  
   
   
       7 . The method recited in  claim 1  wherein at step (c) the multicast transmission of the cache coherence message is also sent to the given processor unit originating the cache coherence message.  
   
   
       8 . Cache-coherence circuitry for a computer architecture having: (a) a shared memory, (b) at least two processor units, each having a processor and cache memory, and (c) a network for communicating cache coherence messages among the processor units and the shared memory, the cache-coherence circuitry comprising: 
 (a) predictive multicasting circuitry, multicasting from a given processor unit, a cache coherence message to a selected set of other processor units, based on a prediction as to which other processor units have cache memories loaded with relevant data; and    (b) a directory detecting insufficiency in the selected set of other processor units to which transmission of the cache coherence message is made, the directory operating upon a detected insufficiency, to retry the multicast transmission of the cache coherence message.    
   
   
       9 . The cache coherence circuitry recited in  claim 8  wherein the directory further, upon repeated insufficiency in the selected set of other processor units, broadcasts the given cache coherence message to all processor units.  
   
   
       10 . The cache coherence circuitry recited in  claim 8  wherein the repeated insufficiency is a predetermined number less than ten.  
   
   
       11 . The cache coherence circuitry recited in  claim 8  wherein the directory sends the retry multicast transmissions to processor units likely to have the relevant data based on a monitoring of cache coherence messages from processor units.  
   
   
       12 . The method of  claim 8  wherein the directory appends a retry number to retires of the cache coherence message.  
   
   
       13 . The method of  claim 12  including circuitry within the processor units responding to the retries appends the retry number to the responses to the retried cache coherence message.  
   
   
       14 . The cache coherence circuitry recited in  claim 8  wherein the predictive multicasting circuitry sends the cache coherence message also to the given processor unit originating the cache coherence message.