Processor control circuit, information processing apparatus, and central processing unit

Abstract

Power consumption by a processor can be reduced without impairing the efficiency of processing by the processor. When a processor 2 inquires the operating status of a DMA controller 4 during a DMA operation, a clock controller 5 stops the supply of a clock signal to the processor 2 to prohibit the processor 2 from making inquiries about the operating status of the DMA controller 4. According to this arrangement, the processor 2 can continue processing until the processor 2 inquires the operating status of the DMA controller 4, that is, until it outputs a state-indication-register-read request signal, even if the DMA operation is being performed in the DMA controller 4. When the processor 2 outputs a state-indication-register-read request signal, the clock signal supply to the processor 2 is stopped.

1 . A processor control circuit comprising: a function unit capable of executing a predetermined process without the intervention of a processor; and a suppressing unit which, when said processor makes an inquiry about the operating status of said function unit during execution of said predetermined process, suppresses operations relating to an inquiry about the operating status of said function unit until said predetermined process ends.  
   
   
       2 . The processor control circuit according to  claim 1 , wherein, when said processor makes an inquiry about the operating status of said function unit during execution of said predetermined process, said suppressing unit delays the operation relating to the inquiry about the operating status of said function unit from said processor until said predetermined process ends.  
   
   
       3 . The processor control circuit according to  claim 1 , wherein, when said processor makes an inquiry about the operating status of said function unit during the execution of said predetermined process, said suppressing unit lowers the frequency of a clock signal being supplied to said processor and maintains the lowered frequency until said predetermined process ends.  
   
   
       4 . The processor control circuit according to  claim 1 , wherein, when said processor makes an inquiry about the operating status of said function unit during execution of said predetermined process, said suppressing unit stops the supply of a clock signal to said processor until said predetermined process ends.  
   
   
       5 . The processor control circuit according to  claim 4 , wherein said suppressing unit is capable of temporarily resuming supplying said clock signal while the supply of said clock signal is stopped.  
   
   
       6 . The processor control circuit according to  claim 5 , wherein, said function unit is capable of executing a Direct Memory Access (DMA) processing and said suppressing unit temporarily resumes the supply of said clock signal every time data of a predetermined length is DMA-transferred while the supply of said clock signal is stopped.  
   
   
       7 . The processor control circuit according to  claim 1 , wherein said function unit comprises a state storage unit for storing execution status information indicating the operating status of said function unit and, when said processor makes an inquiry about said operating status by reading said execution status information, said function unit outputs a read completion signal indicating the completion of the read of said execution status information to said processor to indicate that the predetermined process in said function unit has ended.  
   
   
       8 . An information processing apparatus comprising: a processor executing predetermined processing; a function unit capable of executing a predetermined process without the intervention of said processor; and a suppressing unit which, when said processor makes an inquiry about the operating status of said function unit during execution of said predetermined process, suppresses operations relating to the inquiry about the operating status of said function unit from said processor until said predetermined process ends.  
   
   
       9 . The information processing apparatus according to  claim 8 , wherein, when said processor makes an inquiry about the operating status of said function unit during execution of said predetermined process, said suppressing unit delays the operation relating to the inquiry about the operating status of said function unit from said processor until said predetermined process ends.  
   
   
       10 . The information processing apparatus according to  claim 8 , wherein, when said processor makes an inquiry about the operating status of said function unit during the execution of said predetermined process, said suppressing unit lowers the frequency of a clock signal being supplied to said processor and maintains the lowered frequency until said predetermined process ends.  
   
   
       11 . The information processing apparatus according to  claim 8 , wherein, when said processor makes an inquiry about the operating status of said function unit during the execution of said predetermined process, said suppressing unit stops the supply of a clock signal to said processor until said predetermined process ends.  
   
   
       12 . The information processing apparatus according to  claim 11 , wherein said suppressing unit is capable of temporarily resuming supplying said clock signal while the supply of said clock signal is stopped.  
   
   
       13 . The information processing apparatus according to  claim 12 , wherein: said function unit is capable of executing a Direct Memory Access (DMA) operation and said suppressing unit temporarily supplies said clock signal every time data of a predetermined length is DMA-transferred while the supply of said clock signal is stopped.  
   
   
       14 . The information processing apparatus according to  claim 8 , 
 wherein said function unit comprises a detection condition storage unit for storing detection condition information indicating a detection condition relating to the operating status of said function unit;    said processor writes said detection condition information setting a predetermined condition for detecting the operating status into said detection condition storage unit to make an inquiry about said operating status; and,    when said operating status meets the condition indicated by said detection condition information, said function unit outputs a write completion signal indicating the completion of the write of said detection condition information to said processor to inform that the predetermined process in said function unit has ended.    
   
   
       15 . The information processing apparatus according to  claim 14 , wherein: 
 said function unit is capable of executing a plurality of said predetermined processes;    said processor writes into said detection condition storage unit said detection condition information including information identifying said plurality of processes and the detection condition for detecting an operating status set among said plurality of predetermined processes; and    when an operating status among the predetermines processes that is indicated by said detection condition information meets the detection condition, said function unit outputs said write completion signal to said processor.    
   
   
       16 . A central processing unit comprising a function unit capable of executing a predetermined process without the intervention of a processor; an operation stopping unit for stopping the operation of said processor when said processor makes an inquiry about the execution status of said predetermined process during said predetermined process; an operation resuming unit for causing said processor to resume the operation when said predetermined process ends; an interrupt handling unit for causing said processor to execute interrupt handling when a request for initiating said interrupt handling occurs; and an inquiring unit for inquiring the operating status of said function unit from said processor when said interrupt handling ends.  
   
   
       17 . The central processing unit according to  claim 16 , comprising: a program counter for storing the address of an instruction code to be executed by said processor; and an exception program counter for storing an address obtained by decrementing the address stored in said program counter by one per-instruction-address value; wherein, when said interrupt handling ends, said inquiring unit stores the address stored in said exception program counter into said program counter.