Bipolar transistors with vertical structures

Abstract

A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.

1 - 8 . (canceled)  
   
   
       9 . A method for making a bipolar transistor, comprising: 
 forming a vertical sequence of semiconductor layers, the sequence including a collector layer, a base layer in contact with the collector layer, and an emitter layer in contact with the base layer;    forming an implant mask on a last formed one of the semiconductor layers;    etching the last formed layer to define an intrinsic region of the transistor; and    implanting dopant ions into a portion of one or more of the other semiconductor layers by a process in which the implant mask stops dopant ions from penetrating into a lateral portion of the sequence of layers.    
   
   
       10 . The method of  claim 9 , further comprising: 
 etching away a portion of the last formed one of the of the semiconductor layers by a process in which the implant mask stops a lateral portion of the last formed one of the semiconductor layers from being etched away, and    wherein the act of implanting is performed after the act of etching away.    
   
   
       11 . The method of  claim 9 , wherein the forming a sequence comprises performing a sequence of epitaxial growths of doped semiconductor layers.  
   
   
       12 . The method of  claim 9 , wherein the implanting dopant ions produces a concentration of dopant atoms in the implanted portion that is at least two times higher than a concentration of dopant atoms in the base layer prior to the implanting.  
   
   
       13 . The method of  claim 9 , wherein the implanted portion has a thickness that is greater than the thickness of the base layer.  
   
   
       14 . The method of  claim 9 , further comprising forming an electrode on the implanted portion; and 
 wherein the electrode on the last formed layer of the sequence and the metal electrode on the implanted portion are laterally separated by a gap along a surface of the implanted portion.    
   
   
       15 . The method of  claim 9 , wherein the act of implanting dopant ions includes performing a first implantation of dopant ions with a first energy and then, performing a second implantation of dopant ions with a second energy, the first and second energies being different.  
   
   
       16 . The method of transistor of  claim 9 , wherein each formed layer comprises one of InP, InGaP, InGaAsP, InGaAs, GaAs, InAlGaAs, AlGaAs, GaSb, AlSb, GaAlSb, InSb, InAsSb, GaAsSb, InGaSb, GaN, InN, AlN, InGaN, AlGaN, and InGaAlN.  
   
   
       17 - 27 . (canceled)  
   
   
       28 . A method, comprising: 
 ion implanting a dopant into a semiconductor substrate to form a conductive area therein;    forming a sequence of semiconductor layers on the substrate, the sequence including a collector layer, a base layer in contact with the collector layer, and an emitter layer in contact with the base layer, one of the layers having a bottom surface in contact with the conductive area;    etching away a portion of two of the layers to expose a portion of the one of the layers; and    ion implanting a dopant into the exposed portion to form a conductive channel between the conductive area and a top surface of the exposed portion.    
   
   
       29 . The method of  claim 28 , further comprising treating another portion of the one of the layers to make the another portion nonconductive, the another portion laterally surrounding a device footprint region that includes the implanted portion of the one of the layers.  
   
   
       30 . The method of  claim 28 , wherein the one of the layers is the collector layer and the conductive area is a conducting subcollector connection.  
   
   
       31 . The method of  claim 28 , further comprising: 
 etching the last formed one of the layers to define intrinsic and extrinsic regions of a vertical structure for a bipolar transistor.    
   
   
       32 . The method of  claim 31 , further comprising: 
 ion implanting a dopant into a portion of the base layer to form an implant doped base extension.    
   
   
       33 . The method of  claim 32 , wherein the ion implanting into a portion of the base layer produces in the base extension a concentration of dopant atoms that is at least two times as high as a concentration of dopant atoms in the portion of the base layer in the intrinsic region.  
   
   
       34 . The method of  claim 32 , wherein the base extension is thicker than a portion of the base layer in the intrinsic region.  
   
   
       35 . The method of  claim 28 , wherein the forming a sequence comprises performing a sequence of epitaxial growths of doped semiconductor layers.  
   
   
       36 . The method of  claim 32 , further comprising: 
 forming an electrode on a portion of the last formed one of the semiconductor layers; and    forming an electrode on the base extension; and    wherein the two electrodes are separated by a lateral gap.    
   
   
       37 . The method of  claim 28 , wherein each formed layer comprises one of InP, InGaP, InGaAs, InGaAsP, GaAs, InAlGaAs, AlGaAs, GaSb, AlSb, GaAlSb, InSb, InAsSb, GaAsSb, InGaSb, GaN, InN, AlN, InGaN, AlGaN, and InGaAlN.  
   
   
       38 - 40 . (canceled)