Method for fabrication of semiconductor device

Abstract

A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.

1 .- 10 . (canceled)  
   
   
       11 . A method of fabricating a semiconductor device, comprising the steps of: 
 providing a semiconductor substrate;    forming a borderless logic array, including a plurality of area I/Os, on the semiconductor substrate; and    forming a redistribution layer for redistributing at least some of said area I/Os.    
   
   
       12 . A method according to  claim 11  and also comprising the step of: 
 forming pads to connect said semiconductor device to other devices, wherein at least one of said pads overlays at least a portion of said logic array or a portion of the area I/Os.    
   
   
       13 . A method according to  claim 11  and also comprising the steps of: 
 placing and routing a specific design on said logic array; and    marking marks for an edge of a used portion of said logic array according to the step of placing and routing.    
   
   
       14 . A method according to  claim 13  and wherein said step of marking comprises photolithography, and also comprising a step of dicing said semiconductor substrate according to said marks.  
   
   
       15 . A method according to  claim 14  and wherein said step of dicing comprises laser dicing.  
   
   
       16 . A method according to  claim 11 , further comprising the step of forming a memory array.  
   
   
       17 . A method according to  claim 16  and also comprising the steps of: 
 placing and routing a specific design on said logic array and said memory array; and    marking marks for an edge of a used portion of said logic array and said memory array according to the step of placing and routing.    
   
   
       18 . A method according to  claim 17  and wherein said step of marking comprises photolithography, and also comprising a step of dicing said semiconductor substrate according to said marks.  
   
   
       19 . A method according to  claim 18  and wherein said step of dicing comprises laser dicing.  
   
   
       20 . A method according to  claim 11  and wherein said logic array comprises a module array.  
   
   
       21 . A method according to  claim 16  and wherein said logic array comprises a module array.  
   
   
       22 . A method according to  claim 11 , wherein said logic array is interconnected by metal layers and via layers, and wherein at least one of said metal layers comprises at least one substantially repeating pattern for a portion used for interconnecting.  
   
   
       23 .- 24 . (canceled)  
   
   
       25 . A method according to  claim 11 , further comprising the step of utilizing a direct write technique to customize said logic array.  
   
   
       26 .- 27 . (canceled)  
   
   
       28 . A method according to  claim 11  and wherein said logic array comprises a repeating core, and wherein the step of forming a borderless logic array comprises the step of positioning said area I/Os in a non-surrounding fashion with respect to at least one of said repeating core.  
   
   
       29 . A method according to  claim 11 , wherein said logic array comprises a repeating core, and wherein the step of forming a borderless logic array comprises the step of positioning said area I/Os within said core and wherein at least one of said area I/O is configurable I/O.  
   
   
       30 .- 55 . (canceled)  
   
   
       56 . A method of fabricating a semiconductor device with improved yield, comprising the method of  claim 11 , and further comprising the steps of: 
 testing and marking modules on said logic array;    placing specific designs on said logic array so as to avoid faulty modules;    customizing said logic array according to placement of specific designs;    testing and marking said specific designs; and    dicing said logic array according to placement and marking of specific designs.    
   
   
       57 . A method according to  claim 56 , further comprising the step of utilizing a direct write technique to customize said logic array.  
   
   
       58 .- 62 . (canceled)  
   
   
       63 . A method of fabricating a semiconductor device, comprising: 
 forming a borderless logic array, including a plurality of area I/Os, on the semiconductor substrate, wherein said logic array comprises a repeating core, and wherein at least one of said area I/Os is a configurable I/O, said configurable I/O comprising at least one metal layer that is the same for the various I/O configurations.    
   
   
       64 . A method of fabricating a semiconductor device, comprising: 
 providing a semiconductor substrate; and    forming a borderless logic array, including a plurality of area I/Os, on the semiconductor substrate, wherein said logic array comprises configurable logic, and wherein said configurable logic comprises at least one metal layer that is the same for multiple logic configurations to which the configurable logic may be configured.    
   
   
       65 . A method of fabricating a semiconductor device, comprising: 
 providing a semiconductor substrate; and    forming a borderless logic array, including a plurality of area I/Os, on the semiconductor substrate, wherein said logic array comprises a configurable memory array, and wherein said configurable memory array comprises at least one metal layer that is the same for multiple memory array configurations to which the configurable memory array may be configured.    
   
   
       66 . A method of fabricating a customizable semiconductor device, comprising: 
 providing a semiconductor substrate;    forming a borderless logic array, including a plurality of area I/Os, on the semiconductor substrate; and    utilizing a direct write technique to customize said semiconductor device.    
   
   
       67 . A method of fabricating a semiconductor device, comprising: 
 providing a semiconductor substrate;    forming a borderless logic array, including a plurality of area I/Os, on the semiconductor substrate; and    creating marks to guide a dicing process.