Semiconductor device with a metal insulator semiconductor transistor

Abstract

It is an object to provide a semiconductor device capable of holding multibit information in one memory cell also when scaling for a nonvolatile memory progresses, and a method of manufacturing the semiconductor device. A trench (TR 1 ) is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film ( 122 ) of a gate insulating film ( 120 ) which interpose the trench (TR 1 ) are caused to function as first and second electric charge holding portions capable of holding electric charges (CH 1 ) and (CH 2 ). In the case in which the electric charges (CH 1 ) are trapped and the electric charges (CH 2 ) are then trapped, thus, a portion ( 130 a ) of a gate electrode ( 130 ) in the trench (TR 1 ) functions as a shield. If a fixed potential is given to the gate electrode ( 130 ), the second electric charge holding portion is not influenced by an electric field (EF 1 ) induced by the electric charges (CH 1 ) so that the trapping of the electric charges (CH 2 ) is not inhibited.

1 - 11 . (canceled)  
   
   
       12 . A semiconductor device comprising: 
 a semiconductor substrate having a surface; and    an MIS (Metal Insulator Semiconductor) transistor including a source region formed to face said surface in said semiconductor substrate, a drain region formed to face said surface in said semiconductor substrate apart from said source region, a gate insulating film formed on at least a portion of said surface which is interposed between said source region and said drain region, and a gate electrode formed on said gate insulating film,    wherein first and second electric charge holding portions capable of holding an electric charge are formed in said gate insulating film opposite to each other in such a direction as to connect said source region and said drain region apart from each other,    a thickness of a portion of said gate insulating film which is interposed between said first and second electric charge holding portions is smaller than that of each of portions in which said first and second electric charge holding portions are formed, and    said gate electrode is provided between said first and second electric charge holding portions.    
   
   
       13 . The semiconductor device according to  claim 12 , 
 wherein both of said first and second electric charge holding portions are silicon nitride films, and    a first silicon oxide film, said silicon nitride film and a second silicon oxide film are provided on said semiconductor substrate in this order.    
   
   
       14 . The semiconductor device according to  claim 13 , 
 wherein said portion of said gate insulating film which is interposed between said first and second electric charge holding portions is an extended portion of said first silicon oxide film.    
   
   
       15 . The semiconductor device according to  claim 12 , 
 wherein insulating films are formed between ends of said first and second electric charge holding portions which are opposed to each other and said gate electrode.    
   
   
       16 . The semiconductor device according to  claim 12 , 
 wherein said first and second electric charge holding portions have other ends on said source region and said drain region, respectively.    
   
   
       17 . The semiconductor device according to  claim 16 , 
 wherein insulating films for covering said other ends of said first and second electric charge holding portions are formed on said other ends, respectively.    
   
   
       18 . The semiconductor device according to  claim 12 , 
 wherein both of said first and second electric charge holding portions are formed by a plurality of insular regions in said gate insulating film.    
   
   
       19 . The semiconductor device according to  claim 18 , 
 wherein said insular regions are constituted by silicon or a silicon nitride film.