Digital filter design method and device, digital filter design program, and digital filter

Abstract

A symmetric unit filter (L 10 ″) is designed by combining in series two unit filters ( 1 L 10, 2 L 10 ) having asymmetric numerical sequences as filter coefficients (H 1 to H 3 and H 4 to H 6 ). Thus, by designing a filter by series connection, it is possible to automatically obtain a desired digital filter coefficient only by combining one type of unit filter (L 10 ″) in series. Moreover, a symmetric numerical sequence {−1, 0, 9, 16, 9, 0, −1}/32 is divided at the center into two parts and one of them is used as the asymmetric filter coefficients (H 1 to H 3 and H 4 to H 6 ). This reduces the number of necessary taps, eliminates use of a window function, and prevents generation of a discretization error in the filter characteristic obtained.

1 . A method of designing a digital filter by multiplying signals of taps of a tapped delay line made up of a plurality of delayers several-fold according to given filter coefficients, adding up the results of multiplication and outputting the addition result, comprising: 
 carrying out a filter design using a basic filter formed by cascade connecting first and second unit filters so that the numerical sequence as a whole is symmetric;    said first and second unit filters have asymmetric filter coefficients of numerical sequences whose values are set in such a way that the total values of the respective numerical sequences are non-zeros and the total values of every other values of the numerical sequences match and have the same signs.    
   
   
       2 . The digital filter design method according to  claim 1 , 
 said asymmetric filter coefficients making up said first and second unit filters are formed by dividing a predetermined symmetric numerical sequence at the center into two parts and further adjusting the numerical sequences on both sides; and    the values of said predetermined symmetric numerical sequence are set in such a way that the total value of the numerical sequence is non-zero and the total value of every other values of said numerical sequence match and have the same sign.    
   
   
       3 . The digital filter design method according to  claim 2 , 
 said predetermined symmetric numerical sequence is formed in a ratio of −1, 0, 9, 16, 9, 0, −1; and    said asymmetric filter coefficients form numerical sequences in ratios of −(1−N/8), 0, (9−N/8), 8 and 8, (9−N/8), 0, −(1−N/8) (N: 0≦N≦8).    
   
   
       4 . A method of designing a digital filter by multiplying signals of taps of a tapped delay line made up of a plurality of delayers several-fold according to given filter coefficients, adding up the results of multiplication and outputting the addition result, comprising: 
 carrying out a filter design using a basic filter formed by cascade connecting first and second unit filters so that the numerical sequence as a whole is symmetric;    said first and second unit filters have asymmetric filter coefficients of numerical sequences whose values are set in such a way that the total values of the respective numerical sequences are zeros and the total values of every other values of said numerical sequences match and have the opposite signs.    
   
   
       5 . The digital filter design method according to  claim 4 , 
 asymmetric filter coefficients making up said first and second unit filters are formed by dividing a predetermined symmetric numerical sequence at the center into two parts and further adjusting the numerical sequences on both sides; and    the values of said predetermined symmetric numerical sequence are set in such a way that the total value of the numerical sequence is zero and the total value of every other values of said numerical sequence match and have the opposite sign.    
   
   
       6 . The digital filter design method according to  claim 5 , 
 said predetermined symmetric numerical sequence is formed in a ratio of 1, 0, −9, 16, −9, 0, 1; and    said asymmetric filter coefficients form numerical sequences in ratios of (1−N/8), 0, −(9−N/8), 8 and 8, −(9−N/8), 0, (1−N/8) (N: 0≦N≦8).    
   
   
       7 . The digital filter design method according to  claim 1 , 
 pass frequency band of a filter is adjusted by inserting delays of n clocks between taps corresponding to the asymmetric filter coefficients making up said first and second unit filters.    
   
   
       8 . The digital filter design method according to  claim 4 , 
 pass frequency band of a filter is adjusted by inserting delays of n clocks between taps corresponding to the asymmetric filter coefficients making up said first and second unit filters.    
   
   
       9 . A digital filter design device, comprising: 
 basic filter storing means for storing information related to a basic filter formed by cascade connecting first and second unit filters in such a way that the numerical sequence as a whole is symmetric, said first and second unit filters have asymmetric filter coefficients of a numerical sequence whose values are set so that the total values of the numerical sequences are non-zeros and the total values of every other values of said numerical sequences match and have the same signs;    cascade connecting means for instructing the number of said basic filters cascade connected; and    filter coefficient calculating means for calculating filter coefficients corresponding to the number of filters cascade connected instructed by said cascade connecting means using information stored by said basic filter storing means.    
   
   
       10 . A digital filter design device, comprising: 
 basic filter storing means for storing information related to a basic filter formed by cascade connecting first and second unit filters in such a way that the numerical sequence as a whole is symmetric, said first and second unit filters have asymmetric filter coefficients of a numerical sequence whose values are set so that the total values of the respective numerical sequences are zeros and the total values of every other values of said numerical sequences match and have the opposite signs;    cascade connecting means for instructing the number of said basic filters cascade connected; and    filter coefficient calculating means for calculating filter coefficients corresponding to the number of filters cascade connected instructed by said cascade connecting means using information stored by said basic filter storing means.    
   
   
       11 . The digital filter design device according to  claim 9 , comprising: 
 delay means for adjusting pass frequency band of a filter by inserting delays of n clocks between taps corresponding to the asymmetric filter coefficients making up said first and second unit filters.    
   
   
       12 . The digital filter design device according to  claim 10 , comprising: 
 delay means for adjusting pass frequency band of a filter by inserting delays of n clocks between taps corresponding to the asymmetric filter coefficients making up said first and second unit filters.    
   
   
       13 . A digital filter, comprising: 
 a tapped delay line made up of a plurality of delayers; 
 coefficient multipliers which multiply signals of taps several-fold by filter coefficients calculated using the filter design method according to  claim 1;   
 adders which added up the multiplication results and output the addition result.  
   
   
   
       14 . A digital filter, comprising: 
 a tapped delay line made up of a plurality of delayers;    coefficient multipliers which multiply signals of taps several-fold by filter coefficients calculated using the filter design method according to  claim 4;     adders which added up the multiplication results and output the addition result.    
   
   
       15 . A digital filter including a tapped delay line made up of a plurality of delayers, which multiplies signals of taps several-fold according to given filter coefficients, adds up the multiplication results and outputs the addition result, comprising: 
 forming a basic filter by cascade connecting first and second unit filters so that the numerical sequence as a whole is symmetric, said first and second unit filters have asymmetric filter coefficients of numerical sequences whose values are set in such a way that the total values of the respective numerical sequences are non-zeros and the total values of every other values of the numerical sequences match and have the same sign; and    cascade connecting a plurality of said basic filters.    
   
   
       16 . The digital filter according to  claim 15 , 
 said asymmetric filter coefficients making up said first and second unit filters are formed by dividing a predetermined symmetric numerical sequence at the center into two parts and further adjusting the numerical sequences on both sides; and    the values of said predetermined symmetric numerical sequence are set in such a way that the total value of the numerical sequence is non-zero and the total value of every other values of said numerical sequence match and have the same sign.    
   
   
       17 . The digital filter according to  claim 16 , 
 said predetermined symmetric numerical sequence is formed in a ratio of −1, 0, 9, 16, 9, 0, −1.    
   
   
       18 . The digital filter according to  claim 17 , 
 said asymmetric filter coefficients making up said first and second unit filters form numerical sequences in ratios of −(1−N/8), 0, (9−N/8), 8 and 8, (9−N/8), 0, −(1−N/8) (N: 0≦N≦8).    
   
   
       19 . A digital filter including a tapped delay line made up of a plurality of delayers, which multiplies signals of taps several-fold according to given filter coefficients, adds up the multiplication results and outputs the addition result, comprising: 
 forming a basic filter by cascade connecting first and second unit filters so that the numerical sequence as a whole is symmetric, said first and second unit filters have asymmetric filter coefficients of numerical sequences whose values are set in such a way that the total values of the respective numerical sequences are zeros and the total values of every other values of the numerical sequences match and have the opposite signs; and    cascade connecting a plurality of said basic filters.    
   
   
       20 . The digital filter according to  claim 19 , 
 said asymmetric filter coefficients making up said first and second unit filters are formed by dividing a predetermined symmetric numerical sequence at the center into two parts and further adjusting the numerical sequences on both sides; and    the values of said predetermined symmetric numerical sequence are set in such a way that the total value of the numerical sequence is zero and the total value of every other values of said numerical sequence match and have the opposite sign.    
   
   
       21 . The digital filter according to  claim 20 , 
 said predetermined symmetric numerical sequence is formed in a ratio of 1, 0, −9, 16, −9, 0, 1.    
   
   
       22 . The digital filter according to  claim 21 , 
 said asymmetric filter coefficients making up said first and second unit filters form numerical sequences in ratios of (1−N/8), 0, −(9−N/8), 8 and 8, −(9−N/8), 0, (1−N/8) (N: 0≦N≦8).    
   
   
       23 . The digital filter according to  claim 15 , comprising: 
 delay means for inserting delays of n clocks between taps corresponding to said asymmetric filter coefficients making up said first and second unit filters.    
   
   
       24 . The digital filter according to  claim 19 , comprising: 
 delay means for inserting delays of n clocks between taps corresponding to said asymmetric filter coefficients making up said first and second unit filters.    
   
   
       25 . A digital filter design program for causing a computer to execute processing steps related to the filter design method according to  claim 1 .  
   
   
       26 . A digital filter design program for causing a computer to execute processing steps related to the filter design method according to  claim 4 .  
   
   
       27 . A digital filter design program for causing a computer to function as the means according to  claim 9 .  
   
   
       28 . A digital filter design program for causing a computer to function as the means according to  claim 10