Computer system supporting both dirty-shared and non dirty-shared data processing entities

Abstract

A computer system supports a first set of processors configured to operate in a dirty-shared mode and a second set of processors configured to operate in a non dirty-shared mode. The computer system may include a portion of shared memory that stores data in terms of memory blocks. Upon receiving a snoop read requesting shared access to a memory block held in a dirty state, a dirty-shared processor sends a copy of the memory block to the originator of the snoop read and retains a valid a copy of the block in its cache. Non dirty-shared processors additionally write the block back to main memory in response to snoop reads and may also send a copy to the originator. Until the write back is completed at main memory or another processor is granted write access to the block, the dirty-shared and non dirty-shared processors preferably continue to satisfy subsequent snoop reads targeting the memory block.

1 - 14 . (canceled)  
   
   
       15 . A computer comprising: 
 a plurality of data processing entities;    a main memory accessible by the plurality of data processing entities, the main memory organized to store data in terms of memory blocks, at least one or more of which are shared by the plurality of data processing entities;    means for operating a first data processing entity in a dirty-shared mode, such that the first data processing entity shares with other data processing entities memory blocks that have been modified by the first data processing entity without the first data processing entity writing the modified memory blocks back to the main memory; and    means for operating a second data processing entity in a non dirty-shared mode, such that the second data processing entity, in response to a request by another data processing entity for a memory block that has been modified by the first data processing entity, sends the modified memory block being requested to the main memory.    
   
   
       16 . The computer of  claim 15  wherein the data processing entities include processors.  
   
   
       17 . The computer of  claim 15  wherein 
 the first and second data processing entities each has a respective cache, and    the first and second data processing entities are configured to store memory blocks in their respective caches, and to assign one or more states to each cache-stored memory block.    
   
   
       18 . The computer of  claim 17  wherein the state assigned to each cache-stored memory block includes one of a dirty state and a non dirty state.  
   
   
       19 . The computer of  claim 18  wherein the means for operating the first data processing entity in the dirty-shared mode includes means for sending a copy of a cache-stored memory block that is in the dirty state from the cache to a requesting data processing entity, provided that the dirty memory block is valid.  
   
   
       20 . The computer of  claim 19  wherein the means for operating the first data processing entity in the dirty-shared mode further includes means for marking as shared the dirty memory block that was copied to the requesting data processing entity.  
   
   
       21 . The computer of  claim 15  wherein the means for operating the second data processing entity in the non dirty-shared mode includes means for maintaining, at the second data processing entity, a valid copy of the modified memory block that was sent to the main memory.  
   
   
       22 . The computer of  claim 17  wherein the means for operating the second data processing entity in the non dirty-shared mode includes means for marking the dirty memory block stored at the cache as invalid.  
   
   
       23 . The computer of  claim 15  further comprising one or more directories for use in maintaining coherence of the memory blocks, the one or more directories having an entry for each of a plurality of memory blocks, each directory entry including an owner field for specifying an owner of the memory block, and a writer field for specifying a last data processing entity to have written the memory block back to the main memory.  
   
   
       24 . The computer of  claim 23  wherein each directory entry further includes a sharer field for specifying each data processing entity that has a shared copy of the respective memory block.  
   
   
       25 . A method for use by a computer having a plurality of data processing entities and a main memory configured to store data in terms of memory blocks accessible by the plurality of data processing entities, the method comprising: 
 granting write access over a first memory block to a first data processing entity configured to operate in a non dirty-shared mode, such that the first data processing entity modifies the first memory block;    granting write access over a second memory block to a second data processing entity configured to operate in a dirty-shared mode, such that the second data processing entity modifies the second memory block;    sending a copy of the modified first memory block to the main memory in response to a request that targets the modified first memory block; and    providing a source data processing entity, in response to a request from the source data processing entity for the modified second memory block, with a copy of the modified second memory block, without sending a copy of the modified second memory block to the main memory.    
   
   
       26 . The method of  claim 25  wherein the data processing entities include processors.  
   
   
       27 . The method of  claim 25  further comprising, upon providing a copy of the modified second memory block to the source data processing entity, precluding the second data processing entity from making further modifications to the modified second memory block.  
   
   
       28 . The method of  claim 25  further comprising providing the second data processing entity with a cache for storing memory blocks, wherein the modified second memory block is provided from the cache of the second data processing entity to the source data processing entity.  
   
   
       29 . The method of  claim 25  further comprising providing a second source data processing entity, in response to a request from the second source data processing entity for the modified second memory block, with a copy of the modified second memory block from the cache of the second data processing entity.  
   
   
       30 . The method of  claim 25  further comprising 
 providing the first data processing entity with a cache for storing memory blocks; and    marking as invalid the modified first memory block stored in the cache.    
   
   
       31 . The method of  claim 25  wherein the request for the modified first memory block being issued by a second source data processing entity, the method further comprising: 
 providing the first data processing entity with a cache for storing memory blocks; and    sending the second source data processing entity a copy of the modified first memory block from the cache of the first data processing entity.    
   
   
       32 . The method of  claim 25  further comprising providing one or more directories for use in maintaining coherence of the memory blocks, the one or more directories having an entry for each of a plurality of memory blocks, each directory entry including an owner field for specifying an owner of the memory block, and a writer field for specifying a last data processing entity to have written the memory block back to the main memory.  
   
   
       33 . A method for use by a computer having a plurality of data processing entities and a main memory configured to store data in terms of memory blocks accessible by the plurality of data processing entities, the method comprising: 
 receiving, at a first data processing entity, write access to a first memory block;    storing the first memory block at a cache associated with the first data processing entity;    marking the first memory block stored in the cache of the first data processing entity as valid;    receiving, at a second data processing entity, write access to a second memory block;    storing the second memory block at a cache associated with the second data processing entity;    marking the second memory block stored in the cache of the second data processing entity as valid;    in response to a request for the first memory block, invalidating the first memory block as stored in the cache of the first data processing entity;    providing, in response to a request from a source data processing entity for the second memory block, a copy of the second memory block to the source data processing entity, and    maintaining as valid the second memory block as stored in the cache of the second data processing entity.    
   
   
       34 . The method of  claim 33  wherein the data processing entities include processors.