Semiconductor IC incorporating a co-debugging function and test system

Abstract

A semiconductor IC capable of debugging two or more processors at the same time by means of a single debugger and a semiconductor IC test system. The semiconductor IC includes processors operating at different frequencies, a trigger circuit which causes all of the processors to be in a debugging state when one of the processors is in the debugging state, and a JTAG circuit applying a boundary scan operation to the processors connected to a JTAG pin in series.

1 . A semiconductor integrated circuit (IC) supporting a co-debugging function, comprising: 
 a first processor operating at a first frequency and outputting a first signal indicating whether the first processor is in a debugging state;    a second processor operating at a second frequency different from the first frequency and receiving a second signal adapted to place the second processor in the debugging state;    a trigger circuit receiving the first signal and outputting the second signal, the first signal being received in synchronization with the first frequency and the second signal being synchronized with the second frequency; and,    a joint test action group (JTAG) circuit receiving test data from a JTAG terminal, executing a boundary scan operation of the first and second processors, and outputting test data to the JTAG terminal when the first and second processors are in the debugging state.    
   
   
       2 . The semiconductor IC of  claim 1 , wherein the first processor is a central processing unit (CPU) and the second processor is a digital signal processor (DSP).  
   
   
       3 . The semiconductor IC of  claim 1 , wherein the first processor is a first CPU and the second processor is a second CPU.  
   
   
       4 . The semiconductor IC of  claim 3 , wherein the second processor outputs a third signal indicating whether the second processor is in the debugging state; 
 wherein the trigger circuit receives the third signal and outputs a fourth signal, the third signal being received in synchronization with the second frequency and the fourth signal being synchronized with the first frequency; and,    wherein the fourth signal causes the first processor to assume the debugging state.    
   
   
       5 . The semiconductor IC of  claim 4 , wherein the trigger circuit comprises: 
 a first synchronizing circuit receiving the first signal and outputting the second signal;    a second synchronizing circuit receiving the third signal and outputting the fourth signal; and,    a state machine controlling the first and second synchronizing circuits.    
   
   
       6 . The semiconductor IC of  claim 5 , wherein the state machine causes the second synchronizing circuit to output the fourth signal at a logic level that is not interpreted by the first processor as a debugging request when the first processor is already in the debugging state.  
   
   
       7 . The semiconductor IC of  claim 6 , wherein the first synchronizing circuit comprises: 
 a first flipflop operating in synchronization with a first clock signal, receiving the first signal, and having an output;    a first inverter receiving the output of the first flipflop and having an output;    a first logic gate receiving the first signal and the output of the first inverter and outputting a first pulse signal;    a first series of flipflops operating in synchronization with a second clock signal, receiving a power signal and outputting a second pulse signal;    wherein the first series of flipflops is reset by the first pulse signal;    a second inverter receiving the output of the first series of flipflops and having an output;    a second series of flipflops operating in synchronization with the second clock signal, receiving the output of the second inverter, and outputting a third pulse signal;    a second flipflop operating in synchronization with the second clock signal, receiving the third pulse signal, and outputting a fourth pulse signal;    a third inverter receiving the fourth pulse signal and having an output;    a second logic gate receiving the third pulse signal and the output of the inverter and outputting a first control signal;    a third logic gate receiving the third pulse signal and a second control signal and outputting the second signal; and,    wherein the second series of flipflops and the second flipflop receive a common reset signal.    
   
   
       8 . The semiconductor IC of  claim 6 , wherein the second synchronizing circuit comprises: 
 a first flipflop operating in synchronization with a first clock signal, receiving the third signal, and having an output;    a first inverter receiving the output of the first flipflop and having an output;    a first logic gate receiving the third signal and the output of the first inverter and outputting a first pulse signal;    a first series of flipflops operating in synchronization with a second clock signal, receiving a power signal and outputting a second pulse signal;    wherein the first series of flipflops is reset by the first pulse signal;    a second inverter receiving the output of the first series of flipflops and having an output;    a second series of flipflops operating in synchronization with the second clock signal, receiving the output of the second inverter, and outputting a third pulse signal;    a second flipflop operating in synchronization with the second clock signal, receiving the third pulse signal, and outputting a fourth pulse signal;    a third inverter receiving the fourth pulse signal and having an output;    a second logic gate receiving the third pulse signal and the output of the inverter and outputting a first control signal;    a third logic gate receiving the third pulse signal and a second control signal and outputting the fourth signal; and,    wherein the second series of flipflops and the second flipflop receive a common reset signal.    
   
   
       9 . The semiconductor IC of  claim 1 , wherein the JTAG circuit includes: 
 a test access port (TAP) controller controlling a boundary scan operation; and    a plurality of boundary scan cells connected in series.    
   
   
       10 . A semiconductor integrated circuit (IC) test system, comprising: 
 a debug host executing a debugging operation according to a debugging program;    a host interface converting a signal received from the debug host to a joint test action group (JTAG) interface signal; and    a semiconductor IC receiving the JTAG interface signal from the host interface, wherein the JTAG interface signal causes the semiconductor IC to execute a co-debugging operation.    
   
   
       11 . The semiconductor IC test system of  claim 10 , wherein the semiconductor IC comprises: 
 a first processor operating at a first frequency and outputting a first signal indicating whether the first processor is in a debugging state;    a second processor operating at a second frequency different from the first frequency and receiving a second signal adapted to place the second processor in the debugging state;    a trigger circuit receiving the first signal and outputting the second signal, the first signal being received in synchronization with the first frequency and the second signal being synchronized with the second frequency; and,    a JTAG circuit receiving test data from a JTAG terminal, executing a boundary scan operation of the first and second processors, and outputting test data to the JTAG terminal when the first and second processors are in the debugging state.    
   
   
       12 . The semiconductor IC test system of  claim 11 , wherein the first processor is a central processing unit (CPU) and the second processor is a digital signal processor (DSP).  
   
   
       13 . The semiconductor IC test system of  claim 11 , wherein the first processor is a first CPU and the second processor is a second CPU.  
   
   
       14 . The semiconductor IC test system of  claim 13 , wherein the second processor outputs a third signal indicating whether the second processor is in the debugging state; 
 wherein the trigger circuit receives the third signal and outputs a fourth signal, the third signal being received in synchronization with the second frequency and the fourth signal being synchronized with the first frequency; and,    wherein the fourth signal causes the first processor to assume the debugging state.    
   
   
       15 . The semiconductor IC test system of  claim 14 , wherein the trigger circuit comprises: 
 a first synchronizing circuit receiving the first signal and outputting the second signal;    a second synchronizing circuit receiving the third signal and outputting the fourth signal; and,    a state machine controlling the first and second synchronizing circuits.    
   
   
       16 . The semiconductor IC test system of  claim 15 , wherein the state machine causes the second synchronizing circuit to output the fourth signal at a logic level that is not interpreted by the first processor as a debugging request when the first processor is already in the debugging state.  
   
   
       17 . The semiconductor IC test system of  claim 16 , wherein the first synchronizing circuit comprises: 
 a first flipflop operating in synchronization with a first clock signal, receiving the first signal, and having an output;    a first inverter receiving the output of the first flipflop and having an output;    a first logic gate receiving the first signal and the output of the first inverter and outputting a first pulse signal;    a first series of flipflops operating in synchronization with a second clock signal, receiving a power signal and outputting a second pulse signal;    wherein the first series of flipflops is reset by the first pulse signal;    a second inverter receiving the output of the first series of flipflops and having an output;    a second series of flipflops operating in synchronization with the second clock signal, receiving the output of the second inverter, and outputting a third pulse signal;    a second flipflop operating in synchronization with the second clock signal, receiving the third pulse signal, and outputting a fourth pulse signal;    a third inverter receiving the fourth pulse signal and having an output;    a second logic gate receiving the third pulse signal and the output of the inverter and outputting a first control signal;    a third logic gate receiving the third pulse signal and a second control signal and outputting the second signal; and,    wherein the second series of flipflops and the second flipflop receive a common reset signal.    
   
   
       18 . The semiconductor IC test system of  claim 16 , wherein the second synchronizing circuit comprises: 
 a first flipflop operating in synchronization with a first clock signal, receiving the third signal, and having an output;    a first inverter receiving the output of the first flipflop and having an output;    a first logic gate receiving the third signal and the output of the first inverter and outputting a first pulse signal;    a first series of flipflops operating in synchronization with a second clock signal, receiving a power signal and outputting a second pulse signal;    wherein the first series of flipflops is reset by the first pulse signal;    a second inverter receiving the output of the first series of flipflops and having an output;    a second series of flipflops operating in synchronization with the second clock signal, receiving the output of the second inverter, and outputting a third pulse signal;    a second flipflop operating in synchronization with the second clock signal, receiving the third pulse signal, and outputting a fourth pulse signal;    a third inverter receiving the fourth pulse signal and having an output;    a second logic gate receiving the third pulse signal and the output of the inverter and outputting a first control signal;    a third logic gate receiving the third pulse signal and a second control signal and outputting the fourth signal; and,    wherein the second series of flipflops and the second flipflop receive a common reset signal.    
   
   
       19 . The semiconductor IC test system of  claim 11 , wherein the JTAG circuit includes: 
 a test access port (TAP) controller controlling a boundary scan operation; and    a plurality of boundary scan cells connected in series.