Semiconductor device, method for manufacturing the semiconductor device, and integrated circuit including the semiconductor device

Abstract

A semiconductor device, methods for manufacturing the semiconductor device, and an integrated circuit including the semiconductor device are disclosed. The semiconductor device includes an LDMOS transistor and a MOS transistor, both formed simultaneously on a same substrate. The gate electrodes and the gate oxide layers of the LDMOS and the MOS are formed independently from one another. The source and drain regions of the LDMOS and the MOS are respectively formed in a self-aligned manner. In this way, the LDMOS and the MOS can be formed, in an effective manner, while sustaining the respective desired characteristics.

1 - 37 . (canceled)  
   
   
       38 . A semiconductor device comprising: 
 an LDMOS (lateral double-diffused metal oxide semiconductor) transistor;    an MOS (metal oxide semiconductor) transistor;    a field oxide layer formed between the LDMOS transistor and the MOS transistor, and configured to electrically isolate the LDMOS transistor and the MOS transistor,    wherein the LDMOS transistor comprises: 
 an LDMOS gate electrode, and  
 an LDMOS gate oxide layer;  
   a mitigation oxide layer formed independently from the field oxide layer, between the LDMOS transistor and the MOS transistor, and    wherein the MOS transistor comprises: 
 an MOS gate electrode formed independently from the LMOS gate electrode, and  
 an MOS gate oxide layer formed independently form the LMOS gate oxide layer.  
   
   
   
       39 . The semiconductor device of  claim 38 , wherein a thickness of the LDMOS gate oxide layer and a thickness of the MOS gate oxide layer are different from each other.  
   
   
       40 . The semiconductor device of  claim 38 , wherein a thickness of the LDMOS gate electrode and a thickness of the MOS gate electrode are different from each other.  
   
   
       41 . The semiconductor device of  claim 38 , wherein a thickness of the field oxide layer and a thickness of the mitigation oxide layer are different from each other.  
   
   
       42 . The semiconductor device of  claim 38 , wherein the mitigation oxide layer has a substantially trapezoid cross-sectional shape.  
   
   
       43 . The semiconductor device of  claim 38 , wherein said LDMOS transistor further comprises a well region, a drain well region having a diffusion depth shallower than that of the well region, and a channel well region having a diffusion depth deeper than that of the drain well region.  
   
   
       44 . An integrated circuit, comprising: 
 a voltage regulating circuit, comprising; 
 an input terminal connected to a power supply and configured to receive a voltage from the power supply;  
 a reference voltage generator, including at least one MOS transistor, configured to generate a reference voltage;  
 a resistor configured to divide the input voltage into a divided voltage;  
 an amplifier, including at least one MOS transistor, connected to the reference voltage generator and the resistor, and configured to generate an output voltage based on the comparison between the divided voltage and the reference voltage;  
 an output driver, including at least one LDMOS transistor, connected to the amplifier and configured to output the output voltage;  
 a field oxide layer formed between the LDMOS transistor and the MOS transistor, and configured to electrically isolate the LDMOS transistor and the MOS transistor;  
 an output terminal configured to output the output voltage to the outside,  
 wherein the at least one LDMOS transistor includes: 
 an LDMOS gate electrode, and  
 an LDMOS gate oxide layer;  
 
 a mitigation oxide layer formed independently from the field oxide layer, between the LDMOS transistor and the MOS transistor, and  
 wherein the MOS transistor includes: 
 an MOS gate electrode formed independently from the LMOS gate electrode, and  
 an MOS gate oxide layer formed independently form the LMOS gate oxide layer.  
 
   
   
   
       45 . The integrated circuit of  claim 44 , wherein a thickness of the LDMOS gate oxide layer and a thickness of the MOS gate oxide layer are different from each other.  
   
   
       46 . The integrated circuit of  claim 44 , wherein a thickness of the LDMOS gate electrode and a thickness of the MOS gate electrode are different from each other.  
   
   
       47 . The integrated circuit of  claim 44 , wherein a thickness of the field oxide layer and the thickness of a mitigation oxide layer are different from each other.  
   
   
       48 . The integrated circuit of  claim 44 , wherein the mitigation oxide layer has a substantially trapezoid cross-sectional shape.  
   
   
       49 . The integrated circuit of  claim 44 , wherein said LDMOS transistor further comprises a well region, a drain well region having a diffusion depth shallower than that of the well region, and a channel well region having a diffusion depth deeper than that of the drain well region.