SOI CMOS device with reduced DIBL

Abstract

CMOS devices formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant through openings in a masking layer and through channel regions of the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) diffusion source within the insulation layer underlying the gate regions of the SOI wafer substantially between the source and drain. Backend, high temperature processing steps induce diffusion of the dopants contained in the diffusion source into the p- and n-wells, thereby forming asymmetric retrograde dopant profiles in the channel under the gate. The method can be selectively applied to selected portions of a wafer to tailor device characteristics, such as for memory cells.

1 . Metal-oxide semiconductor (MOS) type transistor devices comprising: 
 a semiconductive substrate;    an insulative layer buried within the semiconductive substrate;    an active layer of semiconductive material above the insulative layer;    a gate structure formed on the active layer; and    source and drain regions formed in the active layer so as to define at least one of n-type (NMOS) and p-type (PMOS) type devices and wherein the insulative layer is provided with a dopant diffusion source localized under the gate structure between the source and drain regions and wherein the dopant diffusion source is diffused into the active layer so as to define a retrograde dopant profile in the active layer under the gate stack substantially between the source and drain regions of the devices.    
   
   
       2 . The devices of  claim 1 , wherein the retrograde dopant profile has a peak concentration substantially adjacent the interface of the insulative layer and the active layer.  
   
   
       3 . The devices of  claim 1 , wherein the retrograde dopant profile provides the devices with improved resistance to drain-induced barrier lowering (DIBL).  
   
   
       4 . The devices of  claim 1 , wherein the retrograde dopant profile in the active layer is asymmetrically positioned with respect to the source and drain regions.  
   
   
       5 . The devices of  claim 4 , wherein the asymmetric retrograde dopant profile is graded laterally between the drain and source regions and provides different threshold voltage and saturation current characteristics of the device as considered between the source to drain regions and between the drain to source regions.  
   
   
       6 . The devices of  claim 4 , wherein the dopant diffusion source and the retrograde dopant profile are offset towards the source region for PMOS devices and towards the drain region for NMOS devices.  
   
   
       7 . The devices of  claim 1 , comprising both the PMOS and the NMOS devices wherein the PMOS and NMOS devices together define complementary (CMOS) device structures.  
   
   
       8 . The devices of  claim 1 , wherein the active layer further comprises threshold adjust dopants positioned substantially between the source and drain regions and under the gate structure.  
   
   
       9 . The device of  claim 1 , wherein the insulative layer with dopant diffusion source comprises borophosphosilicate glass (BPSG).  
   
   
       10 . Complementary metal-oxide semiconductor (CMOS) type transistor devices comprising: 
 a semiconductive substrate;    an insulative layer buried within the semiconductive substrate;    an active layer of semiconductive material above the insulative layer;    gate structures formed on the active layer; and    source and drain regions formed in the active layer so as to define n-type (NMOS) and p-type (PMOS) type devices which together define the CMOS devices and wherein the insulative layer is provided with dopant diffusion sources localized under respective gate structures between the respective source and drain regions and wherein the dopant diffusion sources are diffused into the active layer so as to define corresponding retrograde dopant profiles in the active layer under the respective gate stacks substantially between the source and drain regions of the devices.    
   
   
       11 . The devices of  claim 10 , wherein the retrograde dopant profiles have peak concentrations substantially adjacent the interface of the insulative layer and the active layer.  
   
   
       12 . The devices of  claim 10 , wherein the retrograde dopant profile provides the devices with improved resistance to drain-induced barrier lowering (DIBL).  
   
   
       13 . The devices of  claim 10 , wherein the retrograde dopant profiles in the active layer are asymmetrically positioned with respect to the source and drain regions.  
   
   
       14 . The devices of  claim 13 , wherein the asymmetric retrograde dopant profiles are graded laterally between the drain and source regions and provide different threshold voltage and saturation current characteristics of the devices as considered between the source to drain regions and between the drain to source regions.  
   
   
       15 . The devices of  claim 13 , wherein the dopant diffusion sources and the retrograde dopant profiles are offset towards the source regions for PMOS devices and towards the drain regions for NMOS devices.  
   
   
       16 . The devices of  claim 10 , wherein the active layer further comprises threshold adjust dopants positioned substantially between the source and drain regions and under the gate structure.  
   
   
       17 . The device of  claim 10 , wherein the insulative layer with dopant diffusion source comprises borophosphosilicate glass (BPSG).  
   
   
       18 . A semiconductor transistor device comprising: 
 a semiconductive substrate;    an insulative layer buried within the semiconductive substrate;    an active layer of semiconductive material above the insulative layer;    a gate structure formed on the active layer; and    source and drain regions formed in the active layer wherein the insulative layer is provided with a dopant diffusion source localized under the gate structure between the source and drain regions and wherein the dopant diffusion source is diffused into the active layer so as to define a retrograde dopant profile in the active layer under the gate stack substantially between the source and drain regions.    
   
   
       19 . The device of  claim 18 , wherein the retrograde dopant profile has a peak concentration substantially adjacent the interface of the insulative layer and the active layer.  
   
   
       20 . The device of  claim 18 , wherein the retrograde dopant profile provides the transistor device with improved resistance to drain-induced barrier lowering (DEBL).  
   
   
       21 . The device of  claim 18 , wherein the retrograde dopant profile in the active layer is asymmetrically positioned with respect to the source and drain regions.  
   
   
       22 . The device of  claim 21 , wherein the asymmetric retrograde dopant profile is graded laterally between the drain and source regions and provides different threshold voltage and saturation current characteristics of the device as considered between the source to drain regions and between the drain to source regions.  
   
   
       23 . The device of  claim 18 , wherein the active layer further comprises threshold adjust dopants positioned substantially between the source and drain regions and under the gate structure.  
   
   
       24 . The device of  claim 18 , wherein the insulative layer with dopant diffusion source comprises borophosphosilicate glass (BPSG).