Transistor of volatile memory device with gate dielectric structure capable of trapping charges and method for fabricating the same

Abstract

The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.

1 . A transistor in a cell region of a volatile memory device, the transistor comprising: 
 a substrate of a first conductive type;    a gate dielectric structure capable of trapping charges and formed on the substrate;    a gate formed on the gate dielectric structure;    a gate insulation layer formed on the gate;    a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and    a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.    
   
   
       2 . The transistor of  claim 1 , wherein the gate dielectric structure includes: 
 a bottom gate dielectric layer formed on the substrate;    a middle gate dielectric layer for trapping charges formed on the bottom gate dielectric layer; and    a top gate dielectric layer formed on the middle dielectric layer.    
   
   
       3 . The transistor of  claim 2 , wherein the middle gate dielectric layer is implanted with electrons to increase a threshold voltage value.  
   
   
       4 . The transistor of  claim 2 , wherein the middle dielectric layer is implanted with holes to decrease a threshold voltage value.  
   
   
       5 . The transistor of  claim 2 , wherein the bottom gate dielectric layer and the top gate electric layer are made of oxide and the middle dielectric layer is made of nitride.  
   
   
       6 . The transistor of  claim 2 , wherein the bottom gate dielectric layer and the top gate dielectric layer are made of oxide and the middle gate dielectric layer is made of a material selected from a group consisting of oxynitride, aluminum oxide and hafnium oxide.  
   
   
       7 . A volatile memory device, comprising: 
 a first transistor for use in a memory cell provided with a gate dielectric structure including: 
 a bottom gate dielectric layer;  
 a middle gate dielectric layer for trapping charges; and  
 a top gate dielectric layer; and  
   a second transistor for use in a logic circuit provided with a gate dielectric structure of a single oxide layer.    
   
   
       8 . The volatile memory device of  claim 7 , wherein an effective oxide layer of the gate dielectric structure of the first transistor has a thickness equal to that of an effective oxide layer of the gate dielectric structure of the second transistor.  
   
   
       9 . The volatile memory device of  claim 7 , wherein an effective oxide layer of the gate dielectric structure of the first transistor has a thickness greater than that of an effective oxide layer of the gate dielectric structure of the second transistor.  
   
   
       10 . The volatile memory device of  claim 7 , wherein the middle dielectric layer of the first transistor is implanted with electrons to increase a threshold voltage value.  
   
   
       11 . The volatile memory device of  claim 7 , wherein the middle dielectric layer of the first transistor is implanted with holes to decrease a threshold voltage value.  
   
   
       12 . The volatile memory device of  claim 7 , wherein in the gate dielectric structure of the first transistor, the bottom gate dielectric layer and the top gate dielectric layer are made of oxide and the middle dielectric layer is made of nitride.  
   
   
       13 . The volatile memory device of  claim 7 , wherein in the gate dielectric structure of the first transistor, the bottom gate dielectric layer and the top gate dielectric layer are made of oxide and the middle dielectric layer is made of a material selected from a group consisting of oxynitride, aluminum oxide and hafnium oxide.  
   
   
       14 . A volatile memory device, comprising: 
 a first N-channel metal oxide semiconductor (NMOS) transistor for use in a memory cell provided with a gate dielectric structure including: 
 a bottom gate dielectric layer;  
 a middle gate dielectric layer; and  
 a top gate dielectric layer;  
   a second NMOS transistor for use in a logic circuit provided with a gate dielectric structure of a single oxide layer; and    a P-channel metal oxide semiconductor (PMOS) transistor for use in a logic circuit provided with a gate dielectric structure including: 
 a bottom gate dielectric layer;  
 a middle gate dielectric layer; and  
 a top gate dielectric layer.  
   
   
   
       15 . The volatile memory device of  claim 14 , wherein an effective oxide layer of the gate dielectric structure of the first NMOS transistor and an effective oxide layer of the gate dielectric structure of the PMOS transistor have a thickness equal to that of the gate dielectric structure of the second NMOS transistor.  
   
   
       16 . The volatile memory device of  claim 14 , wherein an effective oxide layer of the gate dielectric structure of the first NMOS transistor and an effective oxide layer of the gate dielectric structure of the PMOS transistor have a thickness greater than that of an effective oxide layer of the gate dielectric structure of the second NMOS transistor.  
   
   
       17 . The volatile memory device of  claim 14 , wherein an effective oxide layer of the gate dielectric structure of the PMOS transistor has a thickness equal to that of an effective oxide layer of the gate dielectric structure of the second NMOS transistor, and an effective oxide layer of the gate dielectric structure of the first NMOS transistor has a thickness greater than that of the effective oxide layer of the gate dielectric structure of the PMOS transistor and that of the effective oxide layer of the gate dielectric structure of the second NMOS transistor.  
   
   
       18 . The volatile memory device of  claim 14 , wherein each middle dielectric layer of the first NMOS transistor and the PMOS transistor is implanted with electrons to increase a threshold voltage.  
   
   
       19 . The volatile memory device of  claim 14 , wherein each middle dielectric layer of the first NMOS transistor and the PMOS transistor are implanted with holes to decrease a threshold voltage.  
   
   
       20 . The volatile memory device of  claim 14 , wherein each bottom gate dielectric layer and each top gate dielectric layer of the first NMOS transistor and the PMOS transistor are made of oxide and each middle gate dielectric layer of the first NMOS transistor and the PMOS transistor is made of nitride.  
   
   
       21 . The volatile memory device of  claim 14 , wherein each bottom gate dielectric layer and each top gate dielectric layer of the first NMOS transistor and the PMOS transistor are made of oxide and each middle gate dielectric layer of the first NMOS transistor and the PMOS transistor is made of a material selected from a group consisting of oxynitride, aluminum oxide and hafnium oxide.  
   
   
       22 . A volatile memory device, comprising: 
 a transistor for use in a memory cell, the transistor including: 
 a substrate of a first conductive;  
 a gate dielectric structure capable of trapping charges and formed on the substrate;  
 a gate formed on the gate dielectric structure;  
 a gate insulation layer formed on the gate;  
 a source/drain of a second conductive type formed in a predetermined portion of the substrate disposed beneath each lateral side of the gate; and  
 a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate; and  
   a voltage generating means for controlling a threshold voltage of the transistor for use in the memory cell by implanting charges to the gate dielectric structure through supplying a predetermined voltage to each of the substrate, the gate and the source/drain.    
   
   
       23 . The volatile memory device of  claim 22 , wherein the gate dielectric structure includes: 
 a bottom gate dielectric layer formed on the substrate;    a middle gate dielectric layer for trapping charges formed on the bottom gate dielectric layer; and    a top gate dielectric layer formed on the middle gate dielectric layer.    
   
   
       24 . The volatile memory device of  claim 23 , wherein the voltage generating means increases a threshold voltage of the transistor for use in the memory cell by implanting electrons to the middle gate dielectric layer.  
   
   
       25 . The volatile memory device of  claim 23 , wherein the voltage generating means decreases a threshold voltage of the transistor for use in the memory cell by implanting holes to the middle gate dielectric layer.  
   
   
       26 . The volatile memory device of  claim 23 , wherein the bottom gate dielectric layer and the top gate dielectric layer are made of oxide and the middle gate dielectric layer is made of nitride.  
   
   
       27 . The volatile memory device of  claim 23 , wherein the bottom gate dielectric layer and the top gate dielectric layer are made of oxide and the middle gate dielectric layer is made of a material selected from a group consisting of oxynitride, aluminum oxide and hafnium oxide.  
   
   
       28 . In a method for forming a gate dielectric structure of a volatile memory device, wherein the volatile memory device is defined with a cell region where a transistor for use in a memory cell is formed and a peripheral region where a transistor for use in a logic circuit is formed, the method comprising the steps of: 
 sequentially forming a first oxide layer, a dielectric layer for trapping charges and a second oxide layer on a substrate;    selectively etching the second oxide layer and the dielectric layer disposed in the peripheral region;    etching the first oxide layer exposed in the peripheral region as simultaneously as etching the second oxide layer in the cell region; and    forming a third oxide layer in the cell region and in the peripheral region.    
   
   
       29 . The method of  claim 28 , wherein at the step of etching the second oxide layer in the cell region, the second oxide layer is controlled to remain with a predetermined thickness so that the gate dielectric structure of the transistor in the cell region includes the first oxide layer, the dielectric layer for trapping charges, the second oxide layer, and the third oxide layer and the gate dielectric structure of the transistor in the peripheral region includes the third oxide layer.  
   
   
       30 . The method of  claim 28 , wherein at the step of etching the second oxide layer in the cell region, the second oxide layer is controlled to remain with a predetermined thickness so that the gate dielectric structure of the transistor in the cell region include the first oxide layer, the dielectric layer for trapping charges and the third oxide layer and the gate dielectric structure of the transistor in the peripheral region includes the third oxide layer.  
   
   
       31 . The method of  claim 28 , wherein the dielectric layer for trapping charges is made of a material selected from a group consisting of nitride, oxynitride, aluminum oxide and hafnium oxide.  
   
   
       32 . In a method for forming a gate dielectric structure in a volatile memory device, wherein the volatile memory device is defined with a cell region where a first NMOS transistor for use in a memory cell is formed and a peripheral region where a second NMOS transistor for use in a logic circuit and a PMOS transistor for use in a logic circuit are formed, the method comprising the steps of: 
 sequentially forming a first oxide layer, a dielectric layer for trapping charges and a second oxide layer on a substrate;    selectively etching the second oxide layer and the dielectric layer in a first predetermined region of the peripheral region where the second NMOS transistor is formed;    removing the first oxide layer exposed in the first predetermined region as simultaneously as etching the second oxide layer disposed in the cell region and in a second predetermined region of the peripheral region where the PMOS transistor is formed; and    forming a third oxide layer in the cell region and in the peripheral region.    
   
   
       33 . The method of  claim 32 , wherein at the step of etching the second oxide layer in the cell region and the first predetermined region of the peripheral region, the second oxide layer is controlled to be etched with a predetermined thickness so that each gate dielectric structure of the first NMOS transistor and the PMOS transistor includes the first oxide layer, the dielectric layer for trapping charges, a remaining portion of the second oxide layer and the third oxide layer and the gate dielectric structure of the second NMOS transistor includes the third oxide layer.  
   
   
       34 . The method of  claim 32 , wherein at the step of etching the second oxide layer in the cell region and the first predetermined region of the peripheral region, the second oxide layer is controlled to remain with a predetermined thickness so that each gate dielectric structure of the first NMOS transistor and the PMOS transistor includes the first oxide layer, the dielectric layer for trapping charges and the third oxide layer and the gate dielectric structure of the second NMOS transistor includes the third oxide layer.  
   
   
       35 . The method of  claim 32 , wherein the dielectric layer for trapping charges is made of a material selected from a group consisting of nitride, oxynitride, aluminum oxide and hafnium oxide.  
   
   
       36 . In a method for forming a gate dielectric structure in a volatile memory device, wherein the volatile memory device is defined with a cell region where a first NMOS transistor for use in a memory cell is formed and a peripheral region where a PMOS transistor for use in a logic circuit and a second NMOS transistor for use in a logic circuit are formed, the method comprising the steps of: 
 sequentially forming a first oxide layer, a dielectric layer for trapping charges and a second oxide layer on a substrate;    selectively etching the second oxide layer and the dielectric layer in a first predetermined region of the peripheral region where the second NMOS transistor is formed;    selectively etching a portion of the second oxide layer in a second predetermined region of the peripheral region where the PMOS transistor is formed to make the second oxide layer have a decreased thickness;    removing the first oxide layer exposed in the first predetermined region as simultaneously as removing the second oxide layer in the second predetermined region and a portion of the second oxide layer in the cell region; and    forming a third oxide layer in the cell region and the peripheral region.    
   
   
       37 . The method of  claim 36 , wherein at the step of etching the second oxide layer in the second predetermined region and in the cell region, the second oxide layer is controlled to be etched with a predetermined thickness, so that the gate dielectric structure of the first NMOS transistor includes the first oxide layer, the dielectric layer for trapping charges, a remaining portion of the second oxide layer and the third oxide layer; the gate dielectric structure of the PMOS transistor includes the first oxide layer, the dielectric layer for trapping charges and the third oxide layer; and the gate dielectric structure of the second NMOS transistor includes the third oxide layer.  
   
   
       38 . The method of  claim 36 , wherein the dielectric layer for trapping charges is made of a material selected from a group consisting of nitride, oxynitride, aluminum oxide and hafnium oxide.