Magnetic random access memory cells having split sub-digit lines having cladding layers thereon and methods of fabricating the same

Abstract

Magnetic RAM cells have split sub-digit lines surrounded by cladding layers and methods of fabricating the same are provided. The magnetic RAM cells include first and second sub-digit lines formed over a semiconductor substrate. Only a bottom surface and an outer sidewall of the first sub-digit line are covered with a first cladding layer pattern. In addition, only a bottom surface and an outer sidewall of the second sub-digit line are covered with a second cladding layer pattern. The outer sidewall of the first sub-digit line is located distal from the second sub-digit line and the outer sidewall of the second sub-digit line is located distal the first sub-digit line. Methods of fabricating the magnetic RAM cells are also provided.

1 . A magnetic random access memory (MRAM) cell, comprising: 
 first and second sub-digit lines formed on a semiconductor substrate;    a first cladding layer pattern covering only a bottom surface and an outer sidewall of the first sub-digit line, the outer sidewall of the first sub-digit line being located distal from the second sub-digit line;    a second cladding layer pattern covering only a bottom surface and an outer sidewall of the second sub-digit line, the outer sidewall of the second sub-digit line being located distal from the first sub-digit line;    a magnetic resistor contact plug penetrating a region between the first and second sub-digit lines; and    a magnetic resistor formed on the magnetic resistor contact plug, wherein the magnetic resistor is electrically connected to the magnetic resistor contact plug.    
     
     
         2 . The MRAM cell as recited in  claim 1 , wherein the first and second cladding layer patterns comprise ferromagnetic layers.  
     
     
         3 . The MRAM cell as recited in  claim 1 , wherein the magnetic resistor comprises a pinning layer, a pinned layer, a tunneling insulating layer and a free layer, which are sequentially stacked.  
     
     
         4 . The MRAM cell as recited in  claim 1 , further comprising: 
 an isolation layer formed at the semiconductor substrate to define an active region; and    an access transistor formed at the active region to have a gate electrode, a source region and a drain region, wherein the magnetic resistor contact plug is electrically connected to the drain region.    
     
     
         5 . The MRAM cell as recited in  claim 4 , wherein the gate electrode crosses over the active region and is parallel with the sub-digit lines.  
     
     
         6 . The MRAM cell as recited in  claim 4 , further comprising a common source line electrically connected to the source region.  
     
     
         7 . The MRAM cell as recited in  claim 6 , wherein the common source line is parallel with the gate electrode.  
     
     
         8 . The MRAM cell as recited in  claim 1 , further comprising: 
 a capping layer covering top surfaces of the first and second sub-digit lines; and    insulating spacers covering inner sidewalls of the first and second sub-digit lines.    
     
     
         9 . The MRAM cell as recited in  claim 1 , further comprising a bit line disposed over the magnetic resistor, wherein the bit line is electrically connected to the magnetic resistor and crosses over the first and second sub-digit lines.  
     
     
         10 . The MRAM cell as recited in  claim 1 , wherein the first and second sub-digit lines extend parallel with each other.  
     
     
         11 . The MRAM cell as recited in  claim 1 , wherein the first and second sub-digit lines extended to come into contact with each other and the first and second sub-digit lines comprise a single digit line and the first and second cladding layer patterns comprise a single cladding layer pattern.  
     
     
         12 . A method of fabricating a magnetic random access memory (MRAM) cell, comprising: 
 forming a first interlayer insulating layer on a semiconductor substrate;    forming a groove in the first interlayer insulating layer;    forming a cladding layer covering a bottom surface and sidewalls of the groove and a digit line filling a space surrounded by the cladding layer;    patterning the digit line and the cladding layer to form an opening that penetrates the digit line and the cladding layer and forms first and second cladding layer patterns at both sides of the opening and first and second sub-digit lines remaining at both sides of the opening;    forming a second interlayer insulating layer on the semiconductor substrate having the opening that separates the first and second sub-digit lines;    forming a magnetic resistor contact plug penetrating the first and second interlayer insulating layers to pass through a region between the first and second sub-digit lines; and    forming a magnetic resistor electrically connected to the magnetic resistor contact plug on the second interlayer insulating layer.    
     
     
         13 . The method as recited in  claim 12 , wherein forming the cladding layer and the digit line comprises: 
 sequentially forming a conformal cladding layer and a conductive layer filling the groove on the semiconductor substrate; and    planarizing the conductive layer and the conformal cladding layer until a top surface of the first interlayer insulating layer is exposed.    
     
     
         14 . The method as recited in  claim 13 , wherein the conformal cladding layer comprises a ferromagnetic layer.  
     
     
         15 . The method as recited in  claim 13 , wherein planarizing the conductive layer and the conformal cladding layer is performed using a chemical mechanical polishing (CMP) process.  
     
     
         16 . The method as recited in  claim 12 , further comprising: 
 forming a capping layer on the semiconductor substrate having the digit lines prior to formation of the first and second sub-digit lines, the capping layer being patterned during formation of the opening; and    forming an insulating spacer on a sidewall of the opening.    
     
     
         17 . The method as recited in  claim 16 , wherein the capping layer and the insulating spacer comprise insulating layers having an etch selectivity with respect to the first and second interlayer insulating layers.  
     
     
         18 . The method as recited in  claim 16 , wherein the capping layer and the insulating spacer comprise a silicon nitride layer.  
     
     
         19 . The method as recited in  claim 12 , further comprising: 
 forming an upper interlayer insulating layer on the semiconductor substrate having the magnetic resistor; and    forming a bit line electrically connected to the magnetic resistor on the upper interlayer insulating layer, wherein the bit line is formed to cross over the sub-digit lines.    
     
     
         20 . The method as recited in  claim 12 , wherein forming the magnetic resistor comprises: 
 sequentially forming a lower electrode layer, a pinning layer, a pinned layer, a tunneling insulation layer, a free layer and an upper electrode layer on the second interlayer insulating layer; and    patterning the upper electrode layer, the free layer, the tunneling insulation layer, the pinned layer, the pinning layer and the lower electrode layer.    
     
     
         21 . The method as recited in  claim 12 , wherein the opening is formed to have a line shape.  
     
     
         22 . The method as recited in  claim 12 , wherein the opening is formed to have a hole shape and the first and second sub-digit lines comprise a single digit line and the first and second cladding layer patterns comprise a single cladding layer pattern.  
     
     
         23 . A method of fabricating a magnetic random access memory (MRAM) cell, comprising: 
 forming a first interlayer insulating layer on a semiconductor substrate;    forming a groove in the first interlayer insulating layer;    forming a conformal cladding layer on the substrate having the groove;    forming a separating wall on a predetermined region of the cladding layer in the groove to divide at least a portion of the groove into first and second grooves;    forming first and second sub-digit lines filling the first and second grooves respectively;    selectively removing the cladding layer on a top surface of the first interlayer insulating layer to form a cladding layer pattern covering only a bottom surface and sidewalls of the groove;    forming a capping layer on the substrate having the sub-digit lines and the cladding layer pattern;    forming an opening penetrating the capping layer, the separating wall and the cladding layer pattern to pass through a region between the first and second sub-digit lines;    forming a spacer covering a sidewall of the opening; and    etching the first interlayer insulating layer using the spacer as an etch mask to form a magnetic resistor contact hole exposing the semiconductor substrate.    
     
     
         24 . The method as recited in  claim 23 , wherein the groove is formed by partially etching the first interlayer insulating layer.  
     
     
         25 . The method as recited in  claim 23 , wherein the cladding layer comprises a ferromagnetic layer.  
     
     
         26 . The method as recited in  claim 23 , wherein forming the separating wall comprises: 
 forming a molding layer on the substrate having the cladding layer;    planarizing the molding layer to form a molding layer pattern in the groove and to expose the cladding layer on the top surface of the first interlayer insulating layer; and    patterning the molding layer pattern.    
     
     
         27 . The method as recited in  claim 23 , wherein the separating wall is formed to have a line shape or an island shape.  
     
     
         28 . The method as recited in  claim 27 , wherein the first and second grooves are defined to be parallel with each other when the separating wall is formed to have the line shape.  
     
     
         29 . The method as recited in  claim 27 , wherein the first and second grooves are connected to each other to form a single merged groove when the separating wall is formed to have the island shape and the first and second sub-digit lines comprise a single digit line and the first and second cladding layer patterns comprise a single cladding layer pattern.  
     
     
         30 . The method as recited in  claim 23 , wherein forming the first and second sub-digit lines comprises: 
 forming a conductive layer filling the first and second grooves on the substrate having the separating wall; and    planarizing the conductive layer and the cladding layer to expose the top surface of the first interlayer insulating layer and a top surface of the separating wall.    
     
     
         31 . The method as recited in  claim 30 , wherein the conductive layer comprises a copper layer.  
     
     
         32 . The method as recited in  claim 30 , wherein the conductive layer and the cladding layer are planarized using a chemical mechanical polishing (CMP) process.  
     
     
         33 . The method as recited in  claim 23 , wherein the capping layer and the spacer comprise insulating layers having an etch selectivity with respect to the first interlayer insulating layer.  
     
     
         34 . The method as recited in  claim 23 , further comprising forming a second interlayer insulating layer on the substrate having the spacer prior to formation of the magnetic resistor contact hole, wherein the magnetic resistor contact hole is formed by etching the first and second interlayer insulating layers using the capping layer and the spacer as etch masks.  
     
     
         35 . The method as recited in  claim 23 , further comprising: 
 forming a magnetic resistor contact plug filling the magnetic resistor contact hole; and    forming a magnetic resistor electrically connected to the magnetic resistor contact plug over the capping layer.    
     
     
         36 . The method as recited in  claim 35 , further comprising: 
 forming an upper interlayer insulating layer on the substrate having the magnetic resistor; and    forming a bit line electrically connected to the magnetic resistor on the upper interlayer insulating layer, wherein the bit line is formed to cross over the sub-digit lines.