Semiconductor device

Abstract

A semiconductor switching device for an inverter includes a first conductivity type, low impurity concentration, semiconductor substrate having a band gap equal to or greater than 2.0 eV, a first conductivity type first region formed in a first plane of the substrate having a resistance lower than the substrate, a first electrode formed in another plane of the first region, a first conductivity type second region formed in a second plane of the substrate, and a second electrode formed on the second region. A trench is formed in the second plane, a control region is formed from a bottom of the trench into the substrate and a control electrode of a different conductivity type is formed on the control region. The second electrode is formed over the control electrode through an insulator film, and the control electrode is formed on the trench sidewalls so the control region contacts the second region.

1 . An inverter apparatus having a semiconductor switching device, the semiconductor switching device including: 
 a first conductivity type substrate comprised of a semiconductor having a band gap equal to or greater than 2.0 eV and having a low impurity concentration;    a first region formed in a first plane of the substrate and having the same first conductivity type as that of the substrate and having a resistance lower than that of the substrate;    a first electrode formed in another plane of the first region;    a second region formed in a second plane of the substrate and having said first conductivity type; and    a second electrode formed on the second region, the semiconductor switching device further comprising:    a trench formed in the second plane;    a control region formed from a bottom of the trench into the substrate and having a different conductivity type than that of the substrate; and    a control electrode formed on the control region,    wherein the second electrode is formed over the control electrode through an insulating film, and    wherein the control region having the different conductivity type from that of the substrate is formed on at least a part of sidewalls of the trench such that the control region is contacted with the second region.    
   
   
       2 . The inverter apparatus according to  claim 1 , 
 wherein an insulating film is formed between the sidewall and the control region of said semiconductor switching device.    
   
   
       3 . The inverter apparatus according to  claim 1 , 
 wherein a width of the control region of said semiconductor switching device is made narrower on the second region side than on the first region side.    
   
   
       4 . The inverter apparatus according to  claim 1 , 
 wherein a plurality of trenches are provided in said semiconductor switching device, each trench having a corresponding control region, and    wherein channel regions are respectively formed between adjacent ones of the control regions.    
   
   
       5 . The inverter apparatus according to  claim 4 , 
 wherein sidewall portions of said semiconductor switching device adjoining the sidewall adjacent ones of the control regions of the trenches are comprised of an MOS channels.    
   
   
       6 . The inverter apparatus according to  claim 1 , 
 wherein the control region of said semiconductor switching device is in contact with the sidewall of the trench is formed with a Schottky contact to provide a MESFET.    
   
   
       7 . The inverter apparatus according to  claim 1 , 
 wherein the second electrode of said semiconductor switching device is formed over an entire surface of the unit device.    
   
   
       8 . An inverter apparatus having a semiconductor switching device, 
 the semiconductor switching device including:    an n-type drift region with a low impurity concentration and a band gap of 2.0 eV or higher;    an n-type drain region formed in a first plane of the drift region and having a lower resistance than the drift region;    a drain electrode formed in another plane of the drain region;    an n-type source region formed in a second plane of the region;    the semiconductor switching device further comprising: 
 a trench formed in the second plane of the drift region;  
 a p-type gate region formed from a bottom of the trench into the drift region; and  
 a gate electrode formed in the gate region,  
 wherein the source electrode is formed over the gate electrode through an insulating film, and  
 wherein the p-type gate region is formed on at least a part of sidewalls of the trench such that the p-type gate is contacted with the source drain.  
   
   
   
       9 . The inverter apparatus according to  claim 1 , 
 wherein a plurality of trenches and a plurality of control regions are provided in said semiconductor switching device, and    wherein a narrowest portion of a channel region present under the second region of said semiconductor switching device and wedged between the control regions is located deeper than bottom portions of the trenches.    
   
   
       10 . The inverter apparatus according to  claim 7 , 
 wherein a plurality of trenches and a plurality of gate regions are provided in said semiconductor switching device and    wherein a narrowest portion of a channel region present under the source region of said semiconductor switching device and wedged between the gate regions is located deeper than bottom portions of the trenches.    
   
   
       11 . The inverter apparatus according to  claim 1 , 
 wherein said control region of said semiconductor switching device extends from the bottom of the trench to the second region to completely cover the sidewalls of the trench.    
   
   
       12 . The inverter apparatus according to  claim 8 , 
 wherein said p-type gate region of said semiconductor switching device extends from the bottom of the trench to the second region to completely cover the sidewalls of the trench.    
   
   
       13 . The inverter apparatus according to  claim 4 , 
 wherein the channel regions of said semiconductor switching device are narrower between areas of the control region adjacent the bottom of the trenches than between areas of the control regions adjacent to the second regions.    
   
   
       14 . The inverter apparatus according to  claim 12 , 
 wherein the channel regions of said semiconductor switching device are narrowest at depth deeper than one half the junction depths formed between the second regions and the substrate.    
   
   
       15 . The inverter apparatus according to  claim 9 , 
 wherein the narrowest part of the channel region of said semiconductor switching device is formed at a depth deeper than one half of a junction depth formed between the control region and the substrate.    
   
   
       16 . The inverter apparatus according to  claim 10 , 
 wherein the narrowest portion of the channel region of said semiconductor switching device is formed at a depth deeper than one half of the junction depth formed between the gate regions and the substrate.