Processor for making more efficient use of idling components and program conversion apparatus for the same

Abstract

A processor that has a plurality of instruction slots each of which stores an instruction to be executed in parallel. One of the plurality of instruction slots is a first instruction slot and another a second instruction slot. A special instruction stored in the first instruction slot is executed by a first functional unit that executes instructions stored in the first instruction slot, and a second functional unit that executes instructions stored in the second instruction slot. An instruction stored in the second instruction slot is executed in parallel by a third functional unit that executes instructions stored in the second instruction slot.

1 - 20 . (canceled)  
     
     
         21 . A processor for executing a plurality of instructions in parallel, comprising: 
 a first functional ,unit, a second functional unit, and a third functional unit each of which is configured to execute an instruction,    wherein the processor is configured to execute a plurality of a first type of instructions in parallel, and a plurality of instructions including a second type of instructions in parallel such that:    when a plurality of a first type of instructions are executed in parallel the first functional unit is capable of executing an instruction in parallel with an execution of another instruction by the second functional unit; and    when a plurality of instructions including a second type of instruction are executed in parallel, the third functional unit is capable of executing an instruction, which is different from the second type of instruction, in parallel with an execution of the second type of instruction by the first functional unit and the second functional unit.    
     
     
         22 . The processor of  claim 21 , wherein the first type of instructions are any types of instruction other than the second type of instruction.  
     
     
         23 . The processor of  claim 22 , further comprising: 
 a plurality of execution groups, the first, second, and third functional units being located in the execution groups;    wherein the first functional unit and the third functional unit are in different execution groups, and    wherein, when a plurality of the first type of instructions are executed in parallel, the third functional unit is capable of executing an instruction in parallel with an execution of another instruction by the first functional unit.    
     
     
         24 . The processor of  claim 23 , wherein the first functional unit and the second functional unit arc in different execution groups.  
     
     
         25 . The processor of  claim 24 , wherein, 
 when a plurality of the first type of instructions arc executed in parallel, functional units in different execution groups are capable of executing the instructions in parallel.    
     
     
         26 . A processing method for executing a plurality of instructions in parallel using a first functional unit, a second functional unit, and a third functional unit, each of the functional units being configured to execute an instruction, the method comprising: 
 executing a plurality of a first type of instructions in parallel, and a plurality of instructions including a second type of instruction in parallel,    when a plurality of a first type of instructions are executed in parallel, the first functional unit executes an instruction in parallel with an execution of another instruction by the second functional unit; and    when a plurality of instructions including a second type of instruction arc executed in parallel, the third functional unit executes an instruction, which is different from the second type of instruction, in parallel with an execution of the second type of instruction by the first functional unit and the second functional unit.    
     
     
         27 . The method of  claim 26 , wherein the first type of instructions are any types of instruction other than the second type of instruction.  
     
     
         28 . The method of  claim 27 , wherein a plurality of execution groups are provided in which the first, second, and third functional units are located, wherein the first functional unit and the third functional unit are in different execution groups, and wherein, when a plurality of the first type of instructions are executed in parallel, the third functional unit executes an instruction in parallel with an execution of another instruction by the first functional unit.  
     
     
         29 . The method of  claim 28 , wherein the first functional unit and the second functional unit are in different execution groups.  
     
     
         30 . The method of  claim 29  wherein, 
 when a plurality of the first type of instructions are executed in parallel functional units in different execution groups execute the instructions in parallel.    
     
     
         31 . The processor of  claim 23  wherein the first type of instructions are standard instructions and the second type instruction is a special instruction.  
     
     
         32 . The processor of  claim 31 , wherein each of the standard instructions requires one functional unit for execution and the special instruction requires two functional units for execution.  
     
     
         33 . The method of  claim 28 , wherein the first type of instructions are standard instructions and the second type of instruction is a special instruction.  
     
     
         34 . The method of  claim 33 , wherein each of the standard instructions requires one functional unit for execution and the special instruction requires two functional units for execution.