Magnitude comparator

Abstract

A magnitude comparator circuit may include a first circuit coupled to receive the operands to be compared, a second circuit coupled to the first circuit, and a third circuit coupled to the second circuit and coupled to receive a first operand of the operands to be compared. The first circuit is configured to generate a vector indicative of whether or not bits in the first operand and the second operand are equal. The second circuit receives the vector, and generates an indication of the first bit, beginning with the most significant bit, at which the first operand and the second operand differ. The third circuit receives the indication, and generates an indication of whether or not the first operand is greater than the second operand. In one embodiment, the first, second, and third circuits are included in a combined magnitude compare/count leading zero circuit.

1 . An apparatus comprising: 
 a first circuit coupled to receive a first operand and a second operand, wherein the first circuit is configured to generate a first vector in response to the first operand and the second operand, and wherein each bit of the first vector is indicative of whether or not the corresponding bits of the first operand and the second operand are equal;    a second circuit coupled to receive the first vector and configured to generate an indication of a most significant bit in which the first operand and the second operand are not equal in response to the first vector; and    a third circuit coupled to receive the indication from the second circuit and the first operand, wherein the third circuit is configured to generate an output indicative of whether or not the first operand is greater than the second operand responsive to the indication and the first operand.    
   
   
       2 . The apparatus as recited in  claim 1  wherein the second circuit comprises a first subcircuit coupled to receive the first vector and generate a second vector, wherein each bit of the second vector is equal to a logical combination of the corresponding bit of the first vector and each more significant bit than the corresponding bit of the first vector.  
   
   
       3 . The apparatus as recited in  claim 2  wherein the first circuit is configured to perform a bitwise exclusive OR, and wherein the logical combination is a logical OR.  
   
   
       4 . The apparatus as recited in  claim 2  wherein the first circuit is configured to perform a bitwise exclusive NOR, and wherein the logical combination is a logical NAND.  
   
   
       5 - 24 . (canceled)