Chip packaging structure

Abstract

A flip-chip package structure includes a flexible interconnection structure, at least one chip, a stiffener layer, and an isolating layer. The flexible interconnection structure having a plurality of bumps on a top surface, a plurality of contact terminals on a bottom surface, and an inner circuit connected to the bumps and the contact terminals. The chip and the stiffener layer are mounted on the top surface of the flexible interconnection structure, and the isolating layer is attached on the bottom surface. The isolating layer includes a plurality of openings that respectively expose the contact terminals of the flexible interconnection structure.

1 . A chip package structure, comprising: 
 a flexible interconnection structure, having a top surface and an opposite bottom surface, the flexible interconnection structure including inner electrical circuits that are electrically connected to a plurality of bumps on the top surface of the flexible interconnection structure and a plurality of contact terminals located on the bottom surface of the flexible interconnection structure, wherein the bumps have a height not larger than 50 μm;    at least one chip, mounted on the top surface of the flexible interconnection structure and electrically connected to the bumps;    a stiffener layer, attached on the top surface of the flexible interconnection structure; and    an isolating layer, attached to the bottom surface of the flexible interconnection structure, the isolating layer including a plurality of openings that respectively expose the contact terminals on the bottom surface of the multilayered interconnection structure, wherein the isolating layer and the flexible interconnection structure are sequentially formed on a base substrate before the chip and the stiffener layer are attached on the top surface of the flexible interconnection structure.    
     
     
         2 . The chip package structure of  claim 1 , wherein the chip is mounted on the top surface of the flexible interconnection structure by a flip-chip type.  
     
     
         3 . The chip package structure of  claim 1 , wherein the stiffener layer includes a stiffener substrate with a hole and a heat sink attached on the stiffener substrate in a manner to cover the hole, wherein the structure of the stiffener substrate and the heat sink results in the cavity of the stiffener layer.  
     
     
         4 . The chip package structure of  claim 3 , wherein the stiffener substrate includes inner circuits that are electrically connected to the inner electrical circuits of the flexible interconnection structure.  
     
     
         5 . The chip package structure of  claim 3 , wherein the stiffener substrate further includes at least one passive component that is embedded therein.  
     
     
         6 . The chip package structure of  claim 3 , wherein the stiffener substrate further includes at least one passive component that is mounted on a surface thereof.  
     
     
         7 . The chip package structure of  claim 1 , wherein the stiffener layer has a cavity that receives the chip therein.  
     
     
         8 . The chip package structure of  claim 7 , wherein the stiffener layer is a heat sink.  
     
     
         9 . The chip package structure of  claim 1 , further comprising at least a passive component formed inside the flexible interconnection structure and electrically connected to the inner electrical circuits.  
     
     
         10 . The chip package structure of  claim 1 , wherein the bumps are selected from the group consisting of Au, Cu, Ni and Sn.  
     
     
         11 . The chip package structure of  claim 10  further comprises a soldering material disposed between the bumps of the flexible interconnection structure and the chip, such that the bumps of the flexible interconnection structure and the chip are electrically connected through a thermal-pressing process.  
     
     
         12 . The chip package structure of  claim 1 , wherein the bumps are made of a soldering material.  
     
     
         13 . The chip package structure of  claim 1 , wherein the base substrate is selected from one of the glass, quartz and ceramics.  
     
     
         14 . The chip package structure of  claim 1 , wherein the contact terminals are a plurality of solder balls.  
     
     
         15 . The chip package structure of  claim 1 , wherein the contact terminals are a plurality of conductive pins.  
     
     
         16 . The chip package structure of  claim 1 , wherein the flexible interconnection structure is formed through a build-up process on the base substrate.  
     
     
         17 . The chip package structure of  claim 1 , wherein the base substrate is removed after the chip and the stiffener layer are attached on the top surface of the flexible interconnection structure.  
     
     
         18 . A method for fabricating the chip package structure of  claim 17 , comprising the following steps: 
 providing the base substrate;    forming the isolating layer on the base substrate;    forming the multi-layered interconnection structure on the isolating layer;    mounting the chip on the top surface of the multi-layered interconnection structure;    attaching the stiffener layer on the top surface of the multi-layered interconnection structure;    removing the base substrate; and    forming the openings of the isolating layer.    
     
     
         19 . The method  claim 18 , wherein the openings of the isolating layer are formed after removing the base substrate.  
     
     
         20 . The method of  claim 18 , wherein the openings of the isolating layer are formed before forming the multi-layered interconnection structure on the isolating layer.