FCBGA package structure

Abstract

The present invention discloses a structure of package. The structure comprises a flip chip solder bumping structure, having a plurality of chips and solder bumps. A substrate has a plurality of conductive lines electrically coupling with the plurality of solder bumps. A print circuit board has a plurality of solder balls electrically coupling with the plurality of conductive lines.

1 . A structure of package, comprising: 
 a substrate having a plurality of conductive lines;    solder bumps electrically coupling with said plurality of conductive lines;    a patterned first elastic dielectric layer covering a partial region of a passivation layer formed on chips;    a conductive layer formed on said patterned first elastic dielectric layer to form a zigzag conductive layer pattern due to the topography of said patterned first elastic dielectric layer, wherein said zigzag conductive layer pattern is partially attached on said passivation layer and partially attached on said first elastic dielectric layer; and    a second elastic dielectric layer covering said conductive layer, said second elastic dielectric layer having a plurality of openings, each of said openings having one of said plurality of solder bumps formed thereon electrically coupling with one of said plurality of conductive lines.    
   
   
       2 . The structure in  claim 1 , further comprising a print circuit board, having a plurality of solder balls electrically coupling with said plurality of conductive lines.  
   
   
       3 . The structure in  claim 2 , further comprising an under-fill material formed among said plurality of solder bumps.  
   
   
       4 . The structure in  claim 1 , wherein said conductive layer at a fixed area of said structure of package will not directly stretch bonding pads of said chips when said solder bumps are placed on said substrate, said zigzag conductive layer pattern acting as a buffer of said structure of package to absorb the stress.  
   
   
       5 . The structure in  claim 1 , further comprising a patterned third elastic dielectric layer formed between said patterned first elastic dielectric layer and said conductive layer.  
   
   
       6 . The structure in  claim 5 , wherein the material of said third elastic dielectric layer comprises BCB, SINR (Siloxane polymer), epoxy, polyimides or resin.  
   
   
       7 . The structure in  claim 1 , wherein the material of said first elastic dielectric layer comprises BCB, SINR (Siloxane polymer), epoxy, polyimides or resin.  
   
   
       8 . The structure in  claim 1 , wherein the material of said passivation layer is polyimides.  
   
   
       9 . The structure in  claim 1 , wherein the material of said conductive layer is metal alloy.  
   
   
       10 . The structure in  claim 9 , wherein said metal alloy comprises Ti/Cu alloy or Cu/Ni/Au alloy.  
   
   
       11 . The structure in  claim 10 , wherein said Ti/Cu alloy is formed by sputtering.  
   
   
       12 . The structure in  claim 10 , wherein said Cu/Ni/Au alloy is formed by electroplating.  
   
   
       13 . The structure in  claim 10 , wherein the thickness of said metal alloy is around 10˜20 micron.  
   
   
       14 . The structure in  claim 4 , wherein the material of said bonding pads comprises Al or Cu.  
   
   
       15 . The structure in  claim 1 , wherein the material of said second elastic dielectric layer comprises BCB, SINR (Siloxane polymer), epoxy, polyimides or resin.  
   
   
       16 . The structure in  claim 4 , wherein said zigzag conductive layer pattern extends from said bonding pad to solder pad under said solder bump, and an included angle between a line segment from center of said chip to center of said solder bump and a radius orientation from said center of said solder bump of said zigzag conductive layer pattern departing from said solder bump is greater than 45° (degrees).  
   
   
       17 . The structure in  claim 16 , wherein said solder bump can be lifted without broken due to performance of said first and second elastic dielectric layer and poor adhesion between said conductive layer and said first and second elastic dielectric layer when the thermal extension of said substrate is higher than said chip.  
   
   
       18 . A conductive bumping arrangement for a package, comprising: 
 a plurality of bonding pads formed on a die; and    a plurality of bumpings formed over said die and connected to said plurality of bonding pads by conductive traces, wherein an included angle between a line segment from center of said die to center of said bumping and a radius orientation from said center of said bumping of said conductive traces departing from said bumping is greater than 45° (degrees).    
   
   
       19 . The bumping arrangement in  claim 18 , wherein said conductive trace extends from a bonding pad to a pad under said bumping.