Highly compact Eprom and flash EEprom devices

Abstract

Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

1 . A method of forming a split-channel electrically programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of: 
 forming on said surface a floating gate having sidewalls and being electrically isolated by a gate dielectric layer from said substrate,    forming a spacer immediately adjacent only one sidewall of said floating gate and extending a controlled distance over said substrate surface,    forming source and drain regions in said substrate by using said floating gate and said spacer as a mask, whereby a channel region is formed in the substrate under the masked region between the source and drain regions,    removing said spacer, and    forming a control gate extending over at least a portion of the floating gate and substrate channel region that was occupied by said spacer, said control gate being electrically insulated from said floating gate and said substrate, whereby a split-channel electrically programmable read only memory transistor is formed.    
   
   
       2 . The method according to  claim 1  wherein the step of forming a spacer immediately adjacent only one sidewall of the floating gate includes the steps of: 
 depositing a thin layer of material over said floating gate and extending a distance beyond said floating gate sidewalls,    anisotropically etching said layer of material for a time to remove it except for first and second portions immediately adjacent opposite sidewalls of said floating gate, and    selectively removing said first portion of material without removal of said second portion, whereby said second portion remains as said spacer.    
   
   
       3 . The method according to  claim 1  wherein the step of forming a spacer immediately adjacent only one sidewall of the floating gate includes the steps of: 
 depositing a thin layer of protective material over said floating gate and extending a distance beyond said floating gate sidewalls,    depositing a relatively thick layer of spacer material over said thin layer and extending a distance beyond said floating gate sidewalls,    anisotropically etching said layer of spacer material for a controlled time to remove it except for first and second portions immediately adjacent opposite sidewalls of said floating gate, said first portion also being positioned adjacent the location of said drain region and said second portion being positioned adjacent the location of said source region, and    selectively removing said first portion of material without removal of either one of said second portion and said protective material layer, whereby said second portion remains as said spacer.    
   
   
       4 . The method according to  claim 2  wherein the step of selectively removing said first portion of material includes the steps of: 
 covering with a masking layer an area including said second portion of material but not said first portion,    etching away said first portion of material, and    removing said masking layer.    
   
   
       5 . The method according to  claim 1  comprising the additional steps of: 
 forming regions of a tunnel erase dielectric layer on each of opposite ends of said floating gate, and    forming a pair of parallel erase gates extending between the source and drain regions and on the tunnel dielectric layers.    
   
   
       6 . The method according to  claim 5  comprising the additional step of forming a second dielectric to insulate the pair of erase gates from said control gate.  
   
   
       7 . The method according to  claim 6  wherein the step of forming the control gate includes forming said control gate to extend over only a portion of said floating gate, thereby leaving a portion of said floating gate that is not covered by the control gate, and wherein the step of forming an erase dielectric layer includes the step of forming said layer over the portion of the floating gate not covered by the control gate without forming said layer over a portion of the floating gate over which the control gate extends.  
   
   
       8 . The method according to  claim 7  wherein the steps of forming the tunnel erase dielectric layer and the erase gates are carried out prior to the steps of forming the second dielectric layer and the control gate.  
   
   
       9 . The method according to  claim 5  wherein the step of forming a region of a tunnel erase dielectric layer on each of opposite ends of said floating gate includes forming the layers on a top surface of the floating gate, and wherein the step of forming a pair of parallel erase gates includes the step of forming each gate over said top surface with at least one of the tunnel dielectric layers therebetween.  
   
   
       10 . The method according to  claim 5  wherein the step of forming a region of a tunnel erase dielectric layer on each of opposite ends of said floating gate includes forming the layers along opposite sidewalls thereof, and wherein the step of forming a pair of parallel erase gates includes the step of forming each gate adjacent one of said sidewalls with one of the tunnel dielectric layers therebetween.  
   
   
       11 . The method according to  claim 5  wherein each of the steps of forming a floating gate, forming a control gate and forming a pair of erase gates include forming their respective gates in a conductive layer that is different from the others.  
   
   
       12 . The method according to  claim 10  which includes an additional step of forming a thin layer of dielectric on said substrate on at least the portions where the erase gates are positioned, and wherein the step of forming the erase gates includes forming said erase gates over said thin dielectric layer.  
   
   
       13 . The method according to  claim 1  which includes an additional step, prior to the step of forming the control gate, of forming an erase gate extending over the floating gate between its side walls with a tunnel dielectric therebetween and across the substrate region that was occupied by the spacer with an insulating layer therebetween, and wherein the step of forming the control gate includes forming the control gate over and around the erase gate over the floating gate and the substrate region that was occupied by the user.  
   
   
       14 . A method of forming a split-channel flash electrically erasable and programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of: 
 forming on said surface a floating gate having opposite sides and opposite ends, said floating gate being electrically insulated from said substrate by a gate dielectric layer,    forming in said substrate a drain region adjacent one side of said floating gate and a source region spaced apart from an opposite side of said floating gate, thereby to form a channel region between the source and drain that has a first channel region under the floating gate a second channel region between the source region and the opposite floating gate side,    forming a control gate extending over at least a portion of the floating gate and said second channel region, said control gate being electrically insulated from said floating gate and said substrate,    forming regions of a tunnel erase dielectric layer on each of opposite ends of said floating gate, and    forming a pair of parallel erase gates extending between the source and drain regions and across the opposite ends of the floating gate on the tunnel dielectric layers.    
   
   
       15 . The method according to  claim 14  wherein the step of forming the control gate includes forming said control gate to extend over only a portion of said floating gate, thereby leaving a portion of said floating gate that is not covered by the control gate, and wherein the step of forming an erase dielectric layer includes the step of forming said layer over the portion of the floating gate not covered by the control gate without forming said layer over a portion of the floating gate over which the control gate extends.  
   
   
       16 . The method according to  claim 14  wherein the step of forming a region of a tunnel erase dielectric layer on each of opposite ends of said floating gate includes forming the layers on a top surface of the floating gate, and wherein the step of forming a pair of parallel erase gates includes the step of forming each gate over said top surface with at least one of the tunnel dielectric layers therebetween.  
   
   
       17 . The method according to  claim 14  wherein the step of forming a region of a tunnel erase dielectric layer on each of opposite ends of said floating gate includes forming the layers along opposite sidewalls thereof, and wherein the step of forming a pair of parallel erase gates includes the step of forming each gate adjacent one of said sidewalls with one of the tunnel dielectric layers therebetween.  
   
   
       18 . The method according to  claim 17  which includes an additional step of forming a thin layer of dielectric on said substrate on at least the portions where the erase gates are positioned, and wherein the step of forming the erase gates includes forming said erase gates over said thin dielectric layer.  
   
   
       19 . The method according to  claim 17  wherein the step of forming the floating gate includes forming its said opposite ends to have edges that are very thin and relatively sharp.  
   
   
       20 . A method of forming a split-channel flash electrically eraseable and programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of: 
 forming on said surface a floating gate having opposite sides and opposite ends, said floating gate being electrically insulated from said substrate by a gate dielectric layer,    forming in said substrate a drain region adjacent one side of said floating gate and a source region spaced apart from an opposite side of said floating gate, thereby to form a channel region between the source and drain that has a first channel region under the floating gate a second channel region between the source region and the opposite floating gate side,    forming a region of a tunnel erase dielectric layer on a portion of the surface of said floating gate,    forming an erase gate extending across the floating gate on the tunnel dielectric layer and across the second channel region of the substrate with a dielectric layer therebetween, and    forming over and around the erase gate a control gate extending across the floating gate and second channel region, said control gate being electrically insulated from said floating gate and said substrate.    
   
   
       21 - 149 . (canceled)