RSFQ Batcher-Banyan switching network

Abstract

Superconductor technology and Batcher banyan switching technology are combined and implemented as a practical component in a single cryo-MCM substrate ( 10 ) containing a plurality of superconductor chips ( 37, 38, 39, 41, 42, 43, 44, 46, 48, 49, 51, 53 and 55 ) arranged in a plurality of rows and columns. Wiring ( 52 ) on the substrate connects the chips in each row of a number of the columns ( 41, 43, 45, 47, 49, 51 & 53 ) serially to collectively define a Batcher sorter. Other wiring ( 52 ) connects the chips in each row of a number of other columns ( 40, 42, 44 & 48 ) in reverse banyan and banyan networks. The foregoing includes a novel superconductor Batcher two-bit serial sorter (FIG. 8 ) and trap (FIG. k 9 ).

1 . A cryogenic Batcher-banyan network, comprising: 
 a substrate, said substrate comprising a predetermined thickness and defining a stiff self-supporting structure;    a plurality of input channels for receiving individual data cells;    a plurality of superconductor chips mounted on said substrate, said superconductor chips being arranged in a plurality of spaced rows and columns on the upper surface of said substrate;    a first one of said plurality of columns of superconductor chips consisting of A type chips;    a second one of said plurality of columns of superconductor chips consisting of C type chips, said second one of said plurality of columns of superconductor chips being located to one side of and immediately adjacent to said first one of said plurality of columns of superconductor chips;    a third one of said plurality of columns of superconductor chips consisting of B type chips, said third one of said plurality of columns of superconductor chips being located to one side of and immediately adjacent to said second one of said plurality of columns of superconductor chips;    a fourth one of said plurality of columns of of superconductor chips consisting of C type chips, said fourth one of said plurality of columns of superconductor chips being located to one side of and immediately adjacent to said third one of said plurality of columns of superconductor chips;    a fifth one of said plurality of columns of of superconductor chips consisting of B type chips, said fifth one of said plurality of columns of superconductor chips being located to one side of and immediately adjacent to said fourth one of said plurality of columns of superconductor chips;    a sixth one of said plurality of columns of superconductor chips consisting of C type chips, said sixth one of said plurality of columns of superconductor chips being located to one side of and immediately adjacent to said fifth one of said plurality of columns of superconductor chips;    a seventh one of said plurality of columns of superconductor chips consisting of C type chips, said seventh one of said plurality of columns of superconductor chips being located to one side of and immediately adjacent to said sixth one of said plurality of columns of superconductor chips;    an eighth one of said plurality of columns of superconductor chips consisting of C type chips, said eighth one of said plurality of columns of superconductor chips being located to one side of and immediately adjacent to said seventh one of said plurality of columns of superconductor chips;    each of said SFQ chips in said first one of said plurality of columns having a plurality of inputs for respectively coupling to said plurality of multiple inputs;    said chips in each of said first one through eighth one of said plurality of columns of superconductor chips defining a plurality of rows of chips with each row comprising in serial order from said first one to said eighth one of said columns an A type chip, a C type chip, a B type chip, a C type chip, a B type chip, a C type chip, a B type chip and a C type chips and each of said chips including multiple inputs and outputs.    said substrate including wiring for coupling the multiple outputs of a chip in each row to the multiple inputs of the next adjacent chip of the row in the next adjacent one of said first through eighth columns to define a Batcher sorter network.    
   
   
       2 . The cryogenic Batcher-banyan network as defined in  claim 1 , wherein said A type chips comprise the topology shown in  FIG. 5  of the drawings; said B type chips comprise the topology shown in  FIG. 6  of the drawings; and said C type chips comprise the topology shown in  FIG. 7  of the drawings.  
   
   
       3 . The cryogenic Batcher-banyan network as defined in  claim 1 , wherein said plurality of superconductor chips further comprises: 
 a ninth one of said plurality of columns of superconductor chips, said ninth one of said plurality of columns of superconductor chips consisting of chips that define a TRAP, said ninth one of said plurality of columns of superconductor chips being located to one side of and immediately adjacent to said eighth one of said plurality of columns of superconductor chips;    each of said chips of said ninth one of said plurality of columns of superconductor chips including multiple inputs and multiple outputs;    said substrate further including wiring for coupling the multiple outputs of said chips in each row of said eighth one of said plurality of columns of superconductor chips to the multiple inputs of the next adjacent chip of the row in said ninth column.    
   
   
       4 . The cryogenic Batcher-banyan network as defined in  claim 3 , wherein said plurality of superconductor chips further comprises: 
 a tenth one of said plurality of columns of superconductor chips consisting of D type chips, said tenth one of said plurality of columns of superconductor chips being located to one side of and immediately adjacent to said ninth one of said plurality of columns of superconductor chips;    an eleventh one of said plurality of columns of superconductor chips consisting of E type chips, said eleventh one of said plurality of columns of superconductor chips being located to one side of and immediately adjacent to said tenth one of said plurality of columns of superconductor chips;    a twelfth one of said plurality of columns of superconductor chips consisting of E type chips, said twelfth one of said plurality of columns of superconductor chips being located to one side of and immediately adjacent to said eleventh one of said plurality of columns of superconductor chips; and    a thirteenth one of said plurality of columns of superconductor chips consisting of D type chips, said thirteenth one of said plurality of columns of superconductor chips being located to one side of and immediately adjacent to said twelfth one of said plurality of columns of superconductor chips;    said chips in each of said tenth one through thirteenth one of said plurality of columns of superconductor chips defining a plurality of rows of chips with each row comprising in serial order from said first one to said eighth one of said columns a D type chip, an E type chip, an E type chip, and a D type chip and each of said chips including multiple inputs and outputs;    said substrate including wiring for coupling the multiple outputs of a chip in each row to the multiple inputs of the next adjacent chip of the row in the next adjacent one of said tenth through thirteenth columns to define a reverse banyan and banyan network.    
   
   
       5 . The cryogenic Batcher-banyan network as defined in  claim 4 , wherein said D type chips comprise the topology shown in  FIG. 7  of the drawings; and said E type chips comprise the topology shown in  FIG. 6  of the drawings.  
   
   
       6 . A SFQ bit-serial sorter for an SFQ Batcher-Banyan network, comprising: 
 first and second inputs for respectively receiving first and second serial data packets, each of said data packets, including a respective multi-bit address located first in serial order within said data packet and with the most significant bits of said respective addresses being first in serial order within said respective address;    a MAX output and a MIN output; and    SFQ means coupled to said first and second inputs for simultaneously receiving said first and second data packets on a bit-by-bit basis, comparing the respective addresses on a bit-by-bit basis to determine the address that comprises the most significant number of the two addresses, and routing said data packet possessing the address comprising the most significant number to said MAX output and the data packet possessing the address comprising a lesser number to said MIN output.    
   
   
       7 - 8 . (canceled)  
   
   
       9 . A trap circuit comprising: 
 an SFQ exclusive OR gate, having a pair of inputs, an output and a clock input for comparing data bits applied to one input of said pair of inputs with that applied concurrently to the second input of said pair of inputs; and, responsive to a clock signal at said clock input, for providing a first output (“1”) when said data bits are dissimilar and producing a second output (“0”) when said data bits are similar, said first output further comprising an SFQ pulse;    an SFQ shift register having a data input, a clock input and an output, said shift register for receiving in serial order and storing a serial bit stream representing an address, said address being formatted so as to have the most significant bits of the address located first in said serial order;    an SFQ non-destructive read-out latch including a data input, a set input and a reset input, and an output, said latch having first and second states;    said first state for preventing SFQ pulses applied to said data input from propagating to said output and said second state for permitting SFQ pulses applied to said data input to propagate to said output;    said latch being set to a first (“0”) state when an SFQ pulse is applied to said reset input and being set to a second (“1”) state when an SFQ pulse is applied to said set input;    an SFQ D-type flip-flop, said SFQ D-type flip-flop having complementary outputs, a data input and a clock input, said SFQ D-type flip-flop having a first and second state for producing an SFQ pulse at said first output when said SFQ D-type flip-flop is in said first state and for producing an SFQ pulse at said second output when said SFQ D-type flip-flop is in said second state;    said data input of said SFQ D-type flip-flop being coupled to said output of said exclusive OR gate for detecting when an SFQ pulse is output from said exclusive OR gate and storing said SFQ pulse;    said first output of said SFQ D-type flip-flop being coupled to said set input of said non-destructive read-out latch;    said second output of said SFQ D-type flip-flop being coupled to said reset input of said non-destructive read-out latch;    said data input of said SFQ non-destructive read-out latch being coupled to said output of said SFQ shift register, wherein digital data that is serially output from said SFQ shift register propagates to said output of said SFQ non-destructive read-out latch only when said latch is in said second state;    means for applying a first serial data stream representing an address of a first data packet to a first input of said exclusive OR gate;    means for applying a second serial data stream representing an address of a second data packet to a second input of said exclusive OR gate, and to said data input of said SFQ shift register;    means for applying clock pulses to said clock input of said exclusive OR gate and to said SFQ shift register; and    means for applying an end of address pulse to said clock input of said SFQ D-type flip-flop, said end of address pulse signifying the completion of transmission of an address to said first and second inputs of said exclusive OR gate, wherein said SFQ D-type flip-flop is read-out and reset to said first state.    
   
   
       10 . The trap circuit as defined in  claim 9 , further comprising: 
 a first splitter and a second splitter, said first and second splitter each including an input and first and second outputs;    said first output of said second splitter being coupled to said second input of said exclusive OR and said second output of said second splitter being coupled to said input of said shift register;    said input of said first splitter for receiving a data cell;    said first output of said first splitter being connected to said input of said second splitter; and    said second output of said first splitter for extending said data cell to an adjacent trap.