US2005246607A1PendingUtilityA1

Coding device and communication system using the same

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Assignee: MOULSLEY TIMOTHY JPriority: Jul 10, 1998Filed: Jul 11, 2005Published: Nov 3, 2005
Est. expiryJul 10, 2018(expired)· nominal 20-yr term from priority
H03M 13/27H04L 1/0071H03M 13/6362H03M 13/2714H03M 13/2792H03M 13/23H03M 13/635H04L 1/0069H04L 1/0009H03M 13/2707H04L 1/0068H03M 13/6356H04L 1/0041H03M 13/13H04L 1/08H03M 13/6558H03M 13/6516H03M 13/6508H03M 13/2957
42
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Claims

Abstract

A coding device includes a coding circuit for converting a digital input into a coded output having a greater number of bits than the input, an interleaving circuit for combining a plurality of words of the coded output and producing therefrom a data block having a plurality of the interleaved words, and a puncturing circuit or repeating circuit for puncturing or repeating bits from the data block. The puncturing or repeating circuit uses a deleting or repeating pattern to provide data words for transmission during respective frames of a transmission channel. The deleting or repeating pattern is selected depending upon the characteristics of the coding circuit and of the interleaving circuit. The coding device is for use in a cordless communication system.

Claims

exact text as granted — not AI-modified
1 . A transmitter for use in a communication system, the transmitter comprising a digital input, a coding device for generating data bits for transmission, and means for transmitting the data bits during respective frames of a transmission channel, wherein the coding device comprises a coding circuit for generating a coded output having a greater number of bits than the digital input, an interleaving circuit for operating on the coded output to generate a data block comprising a plurality of interleaved words, a rate matching circuit for adjusting the number of bits in the data block using a rate matching pattern to provide data bits and means for selecting the rate matching pattern depending on an associated a bit deletion or repetition pattern that is selected to ensure that the deleted or repeated bits of the data block are not required to enable all bits from the digital input to be reconstructed.  
   
   
       2 . (canceled)  
   
   
       3 . A transmitter as claimed in  claim 1 , wherein the rate matching pattern for each interleaved word within the data block is offset with respect to the rate matching pattern of an adjacent interleaved word or words within the block.  
   
   
       4 . A transmitter as claimed in  claim 1 , wherein the rate matching pattern is selected as a function of an interleaving depth of the interleaving circuit.  
   
   
       5 - 10 . (canceled)  
   
   
       11 . A transmitter as claimed in  claim 1 , wherein the coding circuit applies convolutional coding and said means for selecting is selects said rate matching pattern as a function of a constraint length of the convolutional code.  
   
   
       12 . A transmitter as claimed in  claim 1 , further comprising additional coding devices, each for coding a respective digital input, and a multiplexer for combining output data words of said coding device and said additional coding devices for subsequent transmission by the means for transmitting on a single transmission channel.  
   
   
       13 . A transmitter as claimed in  claim 12 , wherein outputs of said coding device and said additional coding devices are selected to have different data rates, the combined data rate corresponding to a channel capacity of the transmission channel.  
   
   
       14 . A transmitter as claimed in  claim 1 , wherein the rate matching pattern forms a matrix including change bits that indicate a change of corresponding bits of said interleaved words within said data block, wherein each row of said matrix includes a maximum of one of said change bits.  
   
   
       15 . A transmitter as claimed in  claim 1 , wherein said coding circuit has one of: (a) a fixed code rate and (b) a predetermined number of rates for a variable data source.  
   
   
       16 . A transmitter as claimed in  claim 1 , wherein said interleaving circuit is not adaptive.  
   
   
       17 . A transmitter as claimed in  claim 1 , wherein said interleaving circuit has a constant input bit rate.  
   
   
       18 . A transmitter as claimed in  claim 1 , wherein said coding circuit has one of: (a) a fixed code rate and (b) a predetermined number of rates for a variable data source, and wherein said interleaving circuit is not adaptive.  
   
   
       19 . A transmitter as claimed in  claim 1 , wherein said rate matching circuit alters a coding rate of said coding circuit according to the bit deletion or repetition pattern.  
   
   
       20 . A receiver for use in a communication system, the receiver comprising means for receiving a coded digital signal comprising a received data block comprising a plurality of interleaved words, the data block having been obtained from a digital input, and processed by a coding device to adjust the number of bits in the data block according to a rate matching pattern, the receiver further comprising a data reconstruction circuit having means for adjusting the number of bits in the data block to reverse the action of the coding device, thereby reconstructing the interleaved words, a de-interleaving circuit having means for generating each of the plurality of interleaved words, a channel decoder, and means for selecting the rate matching pattern as a function of an associated bit deletion or repetition pattern having been selected to ensure that deleted or repeated bits of the data block are not required to enable all bits from the digital input to be reconstructed.  
   
   
       21 . A receiver as claimed in  claim 20 , wherein the rate matching pattern forms a matrix including change bits that indicate a change of corresponding bits of said interleaved words within said received data block, wherein each row of said matrix includes a maximum of one of said change bits.  
   
   
       22 . A receiver as claimed in  claim 20 , wherein said coding device has one of: (a) a fixed code rate and (b) a predetermined number of rates for a variable data source.  
   
   
       23 . A receiver as claimed in  claim 20 , wherein said de-interleaving circuit is not adaptive.  
   
   
       24 . A receiver as claimed in  claim 20 , wherein said de-interleaving circuit has a constant bit rate.  
   
   
       25 . A receiver as claimed in  claim 20 , wherein said coding device has one of: (a) a fixed code rate and (b) a predetermined number of rates for a variable data source, and wherein said de-interleaving circuit is not adaptive.  
   
   
       26 . A receiver as claimed in  claim 20 , wherein a coding rate of said coding circuit is altered according to the bit deletion or repetition rate.  
   
   
       27 . A method of operating a transmitter for use in a communication system, the method comprising operating on a digital input to generate a coded output having a greater number of bits than the digital input, operating on the coded output to generate a data block comprising a plurality of interleaved words and adjusting the number of bits in the data block using a rate matching pattern to provide data bits for transmission during respective frames of a transmission channel, wherein the rate matching pattern is selected as a function of an associated bit deletion or repetition pattern that is selected to ensure that the deleted or repeated bits of the data block are not required to enable all bits from the digital input to be reconstructed.  
   
   
       28 . A method of operating a receiver for use in a communication system, the method comprising receiving a coded digital signal comprising a received data block comprising a plurality of interleaved words, the data block having been obtained from a digital input, and processed to adjust the number of bits in the data block, adjusting the number of bits in the data block according to a rate matching pattern, thereby reconstructing the interleaved words, and de-interleaving and decoding the words to generate an output digital signal, wherein the rate matching pattern is selected as a function of an associated bit deletion or repetition pattern having been selected to ensure that the deleted or repeated bits of the data block are not required to enable all bits from the digital input to be reconstructed.

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