Coding device and communication system using the same

Abstract

A coding device includes a coding circuit for converting a digital input into a coded output having a greater number of bits than the input, an interleaving circuit for combining a plurality of words of the coded output and producing therefrom a data block having a plurality of the interleaved words, and a puncturing circuit or repeating circuit for puncturing or repeating bits from the data block. The puncturing or repeating circuit uses a deleting or repeating pattern to provide data words for transmission during respective frames of a transmission channel. The deleting or repeating pattern is selected depending upon the characteristics of the coding circuit and of the interleaving circuit. The coding device is for use in a cordless communication system.

1 . A rate matching circuit for adjusting the number of bits in a data block, the data block comprising a plurality of interleaved words generated by the action of an interleaving circuit on a coded output generated by the action of a coding circuit on a digital input, the coded output having a greater number of bits than the digital input, the rate matching circuit having means for adjusting the number of bits in the data block using a rate matching pattern to provide data bits for transmission during respective frames of a transmission channel, and means for selecting the rate matching pattern depending on an associated bit deletion or repetition pattern that is selected to ensure that deleted or repeated bits of the data block are not required to enable all bits from the digital input to be reconstructed.  
   
   
       2 . (canceled)  
   
   
       3 . A rate matching circuit as claimed in  claim 1 , wherein the rate matching pattern for each interleaved word within the data block is offset with respect to the rate matching pattern of an adjacent interleaved word or words within the block.  
   
   
       4 . A rate matching circuit as claimed in  claim 1 , wherein the rate matching pattern is selected as a function of an interleaving depth of the interleaving circuit.  
   
   
       5 - 9 . (canceled)  
   
   
       10 . A method of operating a rate matching circuit to adjust the number of bits in a data block, the data block comprising a plurality of interleaved words generated by the action of an interleaving circuit on a coded output generated by the action of a coding circuit on a digital input, the coded output having a greater number of bits than the digital input, the rate matching circuit adjusting the number of bits in the data block using a rate matching pattern to provide data bits for transmission during respective frames of a transmission channel, and selecting the rate matching pattern depending on an associated deletion or repetition pattern that is selected to ensure that the deleted or repeated bits of the data block are not required to enable all bits from the digital input to be reconstructed.  
   
   
       11 . The rate matching circuit of  claim 1 , wherein the rate matching pattern forms a matrix including change bits that indicate a change of corresponding bits of a matrix of said interleaved words within said data block, wherein each row of said matrix formed by the rate matching pattern includes a maximum of one of said change bits.  
   
   
       12 . The rate matching circuit of  claim 1 , wherein said coding circuit has one of: (a) a fixed code rate and (b) a predetermined number of rates for a variable data source.  
   
   
       13 . The rate matching circuit of  claim 1 , wherein said interleaving circuit is not adaptive.  
   
   
       14 . The rate matching circuit of  claim 1 , wherein said interleaving circuit has a constant input bit rate.  
   
   
       15 . The rate matching circuit of  claim 1 , wherein said coding circuit has one of: (a) a fixed code rate and (b) a predetermined number of rates for a variable data source, and wherein said interleaving circuit is not adaptive.  
   
   
       16 . The rate matching circuit of  claim 1 , wherein said rate matching circuit alters a coding rate of said coding circuit according to the bit deletion or repetition pattern.  
   
   
       17 . The method of  claim 10 , wherein said rate matching pattern includes change bits for deleting or repeating bits of said data block and the change bits are offset with respect to each other.  
   
   
       18 . The method of  claim 10 , wherein said rate matching pattern includes change bits for deleting or repeating bits of said data block and the change bits are offset with respect to each other along adjacent columns of a matrix of said rate matching pattern.  
   
   
       19 . The method of  claim 10 , wherein said rate matching pattern includes change bits for deleting or repeating bits of said data block and the change bits are offset with respect to each other along adjacent rows of a matrix of said rate matching pattern.  
   
   
       20 . The method of  claim 10 , wherein said rate matching pattern includes change bits for deleting or repeating bits of said data block and the change bits are offset with respect to each other along adjacent rows and columns of said rate matching pattern.  
   
   
       21 . The method of  claim 10 , wherein said interleaving circuit forms said data block by filling a matrix row by row with row bits of said coded output and outputting column bits of said matrix column by column to form said interleaved words.