Implant-controlled-channel vertical JFET

Abstract

We disclose the structure of an electronic device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has, near the top surface, a buried layer that is electrically communicable to a drain terminal. The device has a body region over the buried layer. A portion of the body region contacts a gate region connected to a gate terminal. The device has a channel region, of which the length spans the distance between the buried layer and a source region, which projects upward from the channel region and is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

1 - 23 . (canceled)  
   
   
       24 . An method for making an electronic device, comprising 
 a. providing a semiconductor substrate of a first conductivity, having a top surface and a bottom surface;    b. forming a buried layer of a second conductivity near the top surface;    c. forming a first semiconductor-layer over the buried layer, doping the region with dopant of the first conductivity;    d. forming in the first layer insulation regions that isolate an island of the first-layer material, the insulation regions having substantially the same thickness as the first layer so the insulation regions reaches the buried layer;    e. forming a second semiconductor-layer of the first conductivity over the first semiconductor-layer and the insulation regions, portions of the second layer over the insulation regions being polycrystalline, portions of the second layer over the first layer being mono-crystalline;    f. forming a dielectric layer over the second layer;    g. implanting dopant of the second conductivity into the island of the first semiconductor layer to form a channel-region in the first and the second semiconductor-layer that reaches the buried layer;    h. forming a third semiconductor-layer of the second conductivity over the dielectric layer;    i. patterning and etching the third semiconductor-layer and the dielectric layer to form a gate structure and uncovering a portion of the second semiconductor-layer; and    j. implanting dopant of the first conductivity into the uncovered second semiconductor-regions to form a gate structure.    
   
   
       25 . The method in  claim 24 , in which the semiconductor substrate is silicon.  
   
   
       26 . The method in  claim 24 , in which the insulation regions comprise silicon dioxide formed with a STI technique.  
   
   
       27 . The method in  claim 24 , in which the first semiconductor layer is about 0.5 micrometers thick and the second semiconductor layer is about 0.2 micrometers thick.  
   
   
       28 . The method in  claim 24 , in which the dielectric layer comprises silicon dioxide and silicon nitride.  
   
   
       29 . The method in  claim 24 , in which the implanting into the first semiconductor layer comprises three implant energies and three implant dosages.  
   
   
       30 . The method in  claim 24 , in which a portion of the dopant implanted into the gate structure diffuses into the mono-crystalline portion of the second semiconductor layer.  
   
   
       31 . The method in  claim 24 , in which the first conductivity is p-type.  
   
   
       32 . The method in  claim 24 , in which the first conductivity is n-type.  
   
   
       33 . A method for making an n-channel silicon JFET, comprising 
 a. providing a p-type silicon substrate, having a top surface and a bottom surface;    b. forming a buried layer of mono-crystalline silicon near the top surface, doped with a n-type dopant to a sheet resistance of about 25 ohms per square;    c. forming a 0.5 micrometers silicon mono-crystalline first layer over the buried layer, doping the region with p-type dopant to a concentration of about 1×10 15  dopant ions per cubic centimeter;    d. forming in the first layer insulation regions that isolate islands of the first-layer material, the insulation regions having substantially the same thickness as the first layer so the insulation regions contact the buried layer;    e. forming a 0.2 micrometer silicon second layer over the first layer and the insulation regions, portions of the second layer over the insulation regions being polycrystalline silicon, portions of the second layer over the first layer being mono-crystalline silicon, doping the second layer with p-type dopant to a concentration of about 1×10 15  dopant ions per cubic centimeter;    f. forming a dielectric layer of silicon dioxide and silicon nitride over the second layer;    g. patterning and etching the dielectric layer to form a opening region free of the dielectric material over the second layer;    h. implanting n-type dopant through the opening region to form a n-type channel-region that reaches the buried layer;    i. forming a third n-type silicon layer over the dielectric layer;    j. patterning and etching the third silicon layer and the dielectric layer to form a source structure and uncovering a portion of the second silicon layer; and    k. implanting p-type dopant into the uncovered second-silicon regions to form a gate structure.