US2005247965A1PendingUtilityA1

Ferroelectric memory device with a conductive polymer layer and a method of formation

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Assignee: ANDIDEH EBRAHIMPriority: Apr 30, 2003Filed: Jul 18, 2005Published: Nov 10, 2005
Est. expiryApr 30, 2023(expired)· nominal 20-yr term from priority
Inventors:Ebrahim Andideh
H10D 1/692G11C 11/22H10B 53/00
42
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Claims

Abstract

A ferroelectric memory device and a method of formation are disclosed. In one particular embodiment, a ferroelectric memory device comprises a first electrode layer formed on a substrate, a ferroelectric polymer layer formed on substantial portion of a first electrode layer, a thin layer of conductive ferroelectric polymer formed on a substantial portion of the ferroelectric polymer layer, where the ferroelectric polymer may be made conductive by doping with conductive nano-particles, and a second electrode layer formed on at least a portion of the carbon doped ferroelectric polymer layer.

Claims

exact text as granted — not AI-modified
1 . A ferroelectric polymer memory device, comprising: 
 a first electrode layer formed on a semiconductor substrate, wherein the first electrode layer has a top surface and a bottom surface;    a ferroelectric polymer layer formed on a substantial portion of the top surface of said first electrode layer;    a conductive ferroelectric polymer layer formed over a substantial portion of said ferroelectric polymer layer; and    a second electrode layer, formed over at least a portion of said conductive ferroelectric polymer layer.    
   
   
       2 . The ferroelectric polymer memory device of  claim 1 , wherein the conductive ferroelectric polymer layer comprises a ferroelectric polymer layer doped with a plurality of nano-particles.  
   
   
       3 . The ferroelectric polymer memory device of  claim 2 , wherein at least a portion of the nano-particles comprise particles of carbon.  
   
   
       4 . The ferroelectric polymer memory device of  claim 3 , wherein a substantial portion of the particles of carbon comprise carbon black.  
   
   
       5 . The ferroelectric polymer memory device of  claim 1 , wherein the semiconductor substrate comprises a complimentary metal oxide semiconductor.  
   
   
       6 . The ferroelectric polymer memory device of  claim 1 , wherein said first and said second electrode layers are substantially formed from one of: titanium nitride (TiN) or tantalum nitride (TaN).  
   
   
       7 . The ferroelectric polymer memory device of  claim 1 , wherein said ferroelectric polymer layer is formed from a copolymer of vinyledene fluoride (VDF) and triflouroethylene (TrFE).  
   
   
       8 . The ferroelectric polymer memory device of  claim 7 , wherein said ferroelectric polymer layer is formed by use of a spin deposition process, to a thickness of approximately 65 nanometers.  
   
   
       9 . The ferroelectric polymer memory device of  claim 1 , wherein said conductive ferroelectric polymer layer comprises a copolymer of vinyledene fluoride (VDF) and triflouroethylene (TrFE), doped with approximately 2-5% by weight of carbon black, and formed to a approximate thickness within the range of 10 nanometers to 50 nanometers.  
   
   
       10 . The ferroelectric polymer memory device of  claim 1 , wherein said first electrode layer and said second electrode layer respectively comprise a plurality of electrodes, formed substantially parallel with respect to each other.  
   
   
       11 . The ferroelectric polymer memory device of  claim 10 , wherein the first and second electrode layer electrodes are formed substantially orthogonal with respect to each other.  
   
   
       12 . A method, comprising: 
 forming a first electrode layer on a substrate, wherein the substrate has a top surface;    forming a ferroelectric polymer layer on a substantial portion of the top surface of said first electrode layer;    forming a conductive ferroelectric polymer layer over at least a portion of said ferroelectric polymer layer, wherein the conductive ferroelectric polymer layer comprises a ferroelectric polymer doped with nano-particles; and    forming a second electrode layer over said conductive ferroelectric polymer layer.    
   
   
       13 . The method of  claim 12 , wherein said first electrode layer is formed from one or more deposition processes, and one or more etching processes.  
   
   
       14 . The method of  claim 13 , wherein said first electrode layer comprises a plurality of electrodes, formed substantially parallel with respect to each other.  
   
   
       15 . The method of  claim 12 , wherein said ferroelectric polymer layer is formed from one or more spin deposition processes.  
   
   
       16 . The method of  claim 12 , wherein said conductive ferroelectric polymer layer is formed from one or more spin deposition processes.  
   
   
       17 . The method of  claim 12 , wherein said second electrode layer is formed from one or more deposition processes, and one or more etching processes.  
   
   
       18 . The method of  claim 12 , wherein said second electrode layer comprises a plurality of electrodes, formed substantially parallel with respect to each other, and formed substantially orthogonal with respect to said first electrode layer.  
   
   
       19 . A method of forming a ferroelectric polymer device, comprising: 
 forming a first plurality of electrodes on a substrate;    forming a first ferroelectric polymer layer over a substantial portion of said first plurality of electrodes, wherein at least a portion of the ferroelectric polymer layer is doped with conductive nano-particles;    forming a second plurality of electrodes over at least a portion of the ferroelectric polymer layer;    forming a second ferroelectric polymer layer over a substantial portion of said second plurality of electrodes, wherein at least a portion of the ferroelectric polymer layer is doped with conductive nano-particles; and    forming a third plurality of electrodes over at least a portion of the ferroelectric polymer layer.    
   
   
       20 . The method of  claim 19 , wherein said forming a first plurality and forming a ferroelectric polymer layer are repeated to form additional electrode layers.  
   
   
       21 . The method of  claim 19 , wherein said first, second and third plurality of electrodes are formed by depositing a metal layer using a physical vapor deposition process, and subsequent patterning of the metal layer into a plurality of electrodes by use of one or more lithography processes.  
   
   
       22 . The method of  claim 19 , wherein the second ferroelectric polymer layer further comprises a layer of ferroelectric polymer doped with nano-particles of carbon black.  
   
   
       23 . An integrated circuit, comprising: 
 a semiconductor layer;    an electrode layer formed on the semiconductor layer;    a ferroelectric polymer layer formed on the electrode layer;    a conductive ferroelectric polymer layer formed on the ferroelectric polymer layer; and    an electrode layer formed on the conductive ferroelectric polymer layer.    
   
   
       24 . The integrated circuit of  claim 23 , wherein the conductive ferroelectric polymer layer comprises a ferroelectric polymer layer doped with a plurality of nano-particles.  
   
   
       25 . The ferroelectric polymer memory device of  claim 24 , wherein at least a portion of the nano-particles comprise particles of carbon.  
   
   
       26 . The ferroelectric polymer memory device of  claim 25 , wherein the particles of carbon comprise carbon black.  
   
   
       27 . The integrated circuit of  claim 23 , wherein said semiconductor layer includes a complimentary metal oxide semiconductor layer.  
   
   
       28 . The integrated circuit of  claim 23 , wherein one or more of said electrode layers include one or more electrodes formed substantially from one of: titanium nitride (TiN) or tantalum nitride (TaN).  
   
   
       29 . The integrated circuit of  claim 23 , wherein said ferroelectric polymer layer includes vinyledene fluoride.  
   
   
       30 . The integrated circuit of  claim 23 , wherein said ferroelectric polymer layer includes trifluoroethylene.  
   
   
       31 . The integrated circuit of  claim 23 , wherein said integrated circuit comprises a polymer memory device.

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