Semiconductor devices having contact plugs with stress buffer spacers and methods of fabricating the same

Abstract

A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.

1 . A semiconductor device comprising: 
 an inorganic insulating layer on a semiconductor substrate;    a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate;    a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer; and    a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug.    
   
   
       2 . The semiconductor device as recited in  claim 1 , further comprising an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.  
   
   
       3 . The semiconductor device as recited in  claim 2 , wherein the etch stop layer comprises a silicon nitride layer.  
   
   
       4 . The semiconductor device as recited in  claim 1 , wherein the inorganic insulating layer comprises a high density plasma (HDP) oxide layer.  
   
   
       5 . The semiconductor device as recited in  claim 1 , wherein the contact plug comprises a single crystal semiconductor plug.  
   
   
       6 . The semiconductor device as recited in  claim 1 , wherein the stress buffer spacer comprises a material that is less dense than the inorganic insulating layer.  
   
   
       7 . The semiconductor device as recited in  claim 6 , wherein the stress buffer spacer comprises a plasma tetra-ethyl-orthosilicate (TEOS) oxide layer.  
   
   
       8 . The semiconductor device as recited in  claim 1 , wherein the TFT comprises spaced-apart source/drain regions in a single crystal silicon pattern disposed on the inorganic insulating layer.  
   
   
       9 . The semiconductor device as recited in  claim 1 , wherein the semiconductor device further comprises: 
 an inter-layer insulating layer covering the TFT; and    a metal plug extending through the inter-layer insulating layer to contact the source/drain region of the TFT and the node contact plug.    
   
   
       10 . A thin film transistor (TFT) static random access memory (SRAM) cell comprising: 
 a driver transistor and a transfer transistor disposed on a semiconductor substrate and connected in series;    an inorganic insulating layer on the semiconductor substrate, covering the driver transistor and the transfer transistor;    a contact plug extending through the inorganic insulating layer to contact a source/drain region shared by the driver transistor and the transfer transistor;    a stress buffer spacer interposed between the contact plug and the inorganic insulating layer; and    a TFT load transistor disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug.    
   
   
       11 . The TFT SRAM cell as recited in  claim 10 , further comprising an etch stop layer underlying the inorganic insulating layer and covering the driver transistor and the transfer transistor, wherein the contact plug extends through the etch stop layer.  
   
   
       12 . The TFT SRAM cell as recited in  claim 11 , wherein the etch stop layer comprises a silicon nitride layer.  
   
   
       13 . The TFT SRAM cell as recited in  claim 10 , wherein the inorganic insulating layer comprises a high density plasma (HDP) oxide layer.  
   
   
       14 . The TFT SRAM cell as recited in  claim 10 , wherein the contact plug comprises a single crystal silicon plug.  
   
   
       15 . The TFT SRAM cell as recited in  claim 10 , wherein the stress buffer spacer comprises a material that is less dense than the inorganic insulating layer.  
   
   
       16 . The TFT SRAM cell as recited in  claim 15 , wherein the stress buffer spacer comprises a plasma tetra-ethyl-orthosilicate (TEOS) oxide layer.  
   
   
       17 . The TFT SRAM cell as recited in  claim 10 , wherein the TFT load transistor comprises spaced-apart source/drain regions in a single crystal silicon pattern disposed on the inorganic insulating layer.  
   
   
       18 . The TFT SRAM cell as recited in  claim 10 , further comprising: 
 an inter-layer insulating layer covering the load transistor; and    a metal plug extending through the inter-layer insulating layer to contact the source/drain region of the TFT load transistor and the contact plug.    
   
   
       19 . A method of fabricating a semiconductor device, comprising: 
 forming an inorganic insulating layer on a semiconductor substrate;    patterning the inorganic insulating layer to form a contact hole exposing a region of the semiconductor substrate;    forming a stress buffer spacer on a sidewall of the node contact hole;    forming a contact plug in the contact hole, the contact plug surrounded by the stress buffer spacer and contacting the exposed region of the semiconductor substrate;    forming a TFT on the inorganic insulating layer, the TFT including a source/drain region extending along the inorganic insulating layer to contact the contact plug.    
   
   
       20 . The method as recited in  claim 19 , further comprising forming an etch stop layer on the semiconductor substrate prior to the formation of the inorganic insulating layer and wherein the contact hole is formed by patterning the inorganic insulating layer and the etch stop layer, the etch stop layer having an etch selectivity with respect to the inorganic insulating layer.  
   
   
       21 . The method as recited in  claim 20 , wherein forming an etch stop layer comprises forming a silicon nitride layer.  
   
   
       22 . The method as recited in  claim 19 , wherein forming an inorganic insulating layer comprises forming a high density plasma (HDP) oxide layer.  
   
   
       23 . The method as recited in  claim 19 , wherein forming the stress buffer spacer comprises: 
 forming a material layer on the semiconductor substrate and conforming to sidewalls of the contact hole, the material layer comprising a material less dense than the inorganic insulating layer; and    anisotropically etching the material layer to expose a bottom surface of the contact hole and the inorganic insulating layer and to leave a portion of the material layer on the sidewall of the node contact hole.    
   
   
       24 . The method as recited in  claim 23 , wherein the material layer comprises a plasma tetra-ethyl-orthosilicate (TEOS) oxide layer.  
   
   
       25 . The method as recited in  claim 19 , wherein forming a contact plug comprises forming the contact plug using a selective epitaxial growth technique.  
   
   
       26 . The method as recited in  claim 19 , wherein forming a TFT comprises: 
 forming an amorphous semiconductor layer or a polycrystalline semiconductor layer on the inorganic insulating layer and the contact plug;    patterning the semiconductor layer to form a semiconductor body pattern on the inorganic insulating layer, the semiconductor body pattern extending along the inorganic insulating layer to contact the contact plug; and    crystallizing the semiconductor body pattern using a solid phase epitaxial process that employs the contact plug as a seed layer.    
   
   
       27 . The method as recited in  claim 19 , wherein forming TFT comprises: 
 forming an amorphous semiconductor layer or a polycrystalline semiconductor layer on the inorganic insulating layer and the contact plug;    crystallizing the semiconductor layer using a solid phase epitaxial process that employs the node contact plug as a seed layer; and    patterning the crystallized semiconductor layer to form a crystallized semiconductor body pattern.    
   
   
       28 . The method as recited in  claim 19 , further comprising: 
 forming an inter-layer insulating layer on the TFT;    patterning the inter-layer insulating layer to form a contact hole exposing the source/drain region of the TFT and the contact plug; and    forming a metal plug filling the contact hole and contacting the source/drain region of the TFT and the contact plug.