Semiconductor device assemblies including an encapsulant located over intermediate conductive elements and filling a space between a semiconductor die and a carrier of the assembly

Abstract

A semiconductor device assembly includes at least one semiconductor die and a carrier. One or more intermediate conductive elements may extend from bond pads of the semiconductor die, through at least one opening through the carrier, to contacts of the carrier. A quantity of dielectric material is disposed between the semiconductor die and the carrier, extends through the at least one opening, and over the at least one intermediate conductive element. The quantity of dielectric material may form a fillet about the periphery of the semiconductor die. The assembly may include a fence on a surface of the carrier opposite from the surface next to which the semiconductor die is positioned. Such a fence may laterally contain a portion of the quantity of dielectric material, which may have a substantially planar exposed surface.

1 . A semiconductor device assembly comprising: 
 at least one semiconductor die having an active surface with at least one bond pad exposed thereon, a back surface, and peripheral edges;    a carrier substrate adjacent to the at least one semiconductor die and having a first surface with at least one contact pad exposed thereon, a second surface, and an opening between the first and second surfaces;    a dam on the first surface of the carrier substrate around the at least one contact pad and the opening;    at least one intermediate conductive element extending between the at least one bond pad and the at least one contact pad;    at least one adhesive element disposed between the at least one semiconductor die and the carrier substrate, the at least one adhesive element spacing the carrier substrate and the at least one semiconductor die apart from each other;    a dielectric filler material disposed between the at least one semiconductor die and the carrier substrate, wherein the dielectric filler material at least partially fills the opening, is laterally contained by the dam, and encapsulates the at least one intermediate conductive element.    
     
     
         2 . The semiconductor assembly of  claim 1 , wherein an exposed surface of the dielectric filler material within the dam is substantially level.  
     
     
         3 . The semiconductor assembly of  claim 1 , wherein the dielectric filler material encapsulates the peripheral edges of the at least one semiconductor die.  
     
     
         4 . The semiconductor assembly of  claim 1 , wherein the dielectric filler material encapsulates the back surface of the at least one semiconductor die.  
     
     
         5 . The semiconductor assembly of  claim 1 , wherein a dielectric material different than the dielectric filler material encapsulates the back surface of the at least one semiconductor die.  
     
     
         6 . The semiconductor assembly of  claim 1 , wherein the at least one adhesive element comprises a plurality of substantially symmetrically arranged adhesive elements.  
     
     
         7 . The semiconductor assembly of  claim 6 , wherein the plurality of adhesive elements comprises a plurality of adhesive elements that are mutually separate and discrete from each other.  
     
     
         8 . The semiconductor assembly of  claim 7 , wherein at least some of the plurality of adhesive elements are positioned proximate at least corner portions of the at least one semiconductor die.  
     
     
         9 . The semiconductor assembly of  claim 7 , wherein at least some of the plurality of adhesive elements are positioned proximate at least one of the peripheral edges of the at least one semiconductor die.  
     
     
         10 . The semiconductor assembly of  claim 7 , wherein the plurality of adhesive elements comprises adhesive point pads.  
     
     
         11 . The semiconductor assembly of  claim 6 , wherein the plurality of adhesive elements comprises elongated pads mutually separate and discrete from each other.  
     
     
         12 . The semiconductor assembly of  claim 11 , wherein the elongated pads are positioned laterally adjacent the opening and extend substantially parallel thereto.  
     
     
         13 . The semiconductor assembly of  claim 11 , wherein the elongated pads are positioned laterally adjacent the opening and extend substantially transverse thereto.  
     
     
         14 . The semiconductor assembly of  claim 6 , wherein the plurality of adhesive elements comprises at least one of a decal, a tape segment, and a volume of adhesive.  
     
     
         15 . The semiconductor assembly of  claim 1 , wherein the at least one semiconductor die comprises one or more semiconductor dice.  
     
     
         16 . The semiconductor assembly of  claim 1 , wherein the carrier substrate comprises at least one of a BT resin, a ceramic material, a polymeric material, an FR-4 material, and an FR-5 material.  
     
     
         17 . A semiconductor device assembly comprising: 
 a carrier with at least one opening therethrough;    at least one semiconductor die positioned adjacent to a surface of the carrier and superimposed with respect to the at least one opening;    at least one intermediate conductive element extending from a bond pad of the at least one semiconductor die, through the at least one opening, to a contact on an opposite surface of the carrier; and    a quantity of encapsulant material that lacks discernable internal boundaries extending between the carrier and the at least one semiconductor die, through the opening, and over the at least one intermediate conductive element.    
     
     
         18 . The semiconductor device assembly of  claim 17 , further comprising: 
 at least one dam protruding from the opposite surface of the carrier and laterally containing at least a portion of the quantity of encapsulant material.    
     
     
         19 . The semiconductor device assembly of  claim 18 , wherein the at least one dam substantially surrounds the at least one opening.  
     
     
         20 . The semiconductor device assembly of  claim 17 , wherein an exposed surface of the quantity of encapsulant material located over the opposite surface of the carrier is substantially planar.