Accessing a test condition

Abstract

A method and system of executing computer instructions is described. Each instruction defines first and second operands and an operation to be carried out on said operands. Each instruction also contains an address field of a predetermined bit length which identifies a test register holding a plurality of test bits greater than the predetermined bit length. The test register holds a test code defining a test condition. The test condition is checked against at least one condition code and the operation is selectively carried out in dependence on whether the condition code satisfies the test condition. In one embodiment, the condition codes are set on a lane-by-lane basis for packed operands.

1 . A method for conditionally executing operations contained in an instruction, the method comprising: 
 (a) executing a first operation in a first instruction to generate a set of condition codes;    (b) in a second instruction having a test register field, selecting a test code from a test register defined by an address in the test register field, the test code defining a test condition;    (c) checking the defined test condition against the set of condition codes; and    (d) selectively executing a second operation in the second instruction only when the condition codes generated by the first instruction satisfy the test condition defined in the second instruction.    
   
   
       2 . The method of  claim 1 , wherein the test condition has a greater number of bits than the test register field.  
   
   
       3 . The method of  claim 1 , wherein the first and second instruction further includes fields defining a first and second operand, and wherein operations are executed upon the first and second operands.  
   
   
       4 . The method of  claim 3 , wherein the first operand and second operand each contain a plurality of packed objects in respective lanes, wherein step (c) further comprises checking the test condition against a condition code for each lane of the first or second operand, and step (d) further comprises executing the operation only in those lanes in which the condition code satisfies the test condition.  
   
   
       5 . The method of  claim 1 , wherein a bit length of the test register field is three bits long, wherein the test register comprises a test code having four bits, a condition code selector having three bits, and a single side field bit.  
   
   
       6 . The method of  claim 5 , wherein the single side field bit denotes which set of condition codes are to be accessed where there are dual execution channels, each having an associated set of condition codes.  
   
   
       7 . A computer system for conditionally executing an operation included in a computer instruction, the computer system comprising: 
 memory means for storing first and second instructions, the instructions each defining a test register field and an opcode field;    means for identifying a test register based on an address in the test register field, the test register having a test code that defines a test condition;    computer processing means for executing an operation defined in the opcode field of the first instruction, wherein said execution of the first instruction generates a set of condition codes; and    means for checking at least one condition code against a test condition defined in the second instruction;    wherein an operation defined in the opcode field of the second instruction, is executed when the condition code generated by the execution of the first instruction satisfies the test condition defined in the second instruction.    
   
   
       8 . The system of  claim 7 , wherein the test condition has a greater number of bits than the test register field.  
   
   
       9 . The system of  claim 7 , wherein the instructions further include fields defining a first and second operand, and wherein the operations are conditionally executed upon the first and second operands.  
   
   
       10 . The system of  claim 9 , wherein the first operand and second operand each contain a plurality of packed objects in respective lanes, and wherein the checking means further included means for checking the test condition against a condition code for each lane of the first or second operand, and further comprising computer processing means for executing the operation only in those lanes in which the condition code satisfies the test condition.  
   
   
       11 . The system of  claim 7 , wherein the bit length of the test register field is three bits long, wherein the test register comprises a test code having four bits, a condition code selector having three bits, and a single side field bit.  
   
   
       12 . The system of  claim 11 , wherein the single side field bit denotes which set of condition codes are to be accessed where the computer system has dual execution channels, each channel having an associated set of condition codes.