Semiconductor device and method of fabricating the same

Abstract

A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device includes a substrate, a thin film transistor formed on the substrate and having a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric, and a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer. The contact hole has a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of the wet etch profile and a dry etch profile.

1 . A semiconductor device, comprising: 
 a substrate;    a thin film transistor formed on the substrate and including a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric; and    a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer, and having a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of a wet etch profile and a dry etch profile.    
     
     
         2 . The semiconductor device of  claim 1 , wherein the wet etch profile in the upper portion of the contact hole has a taper angle in a range of about 5° to about 60°.  
     
     
         3 . The semiconductor device of  claim 1 , wherein the wet etch profile in the upper portion of the contact hole has a taper angle in a range of about 5° to about 45°.  
     
     
         4 . The semiconductor device of  claim 1 , wherein the dry etch profile has a taper angle in a range of about 60° to about 90°.  
     
     
         5 . The semiconductor device of  claim 1 , wherein the dry etch profile has a taper angle in a range of about 75° to about 90°.  
     
     
         6 . The semiconductor device of  claim 1 , wherein the dry etch profile includes a high selectivity dry etch profile and a high etch rate dry etch profile.  
     
     
         7 . A method of fabricating a semiconductor device, comprising: 
 forming a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric on a substrate;    performing at least one of a dry etching process and a wet etching process on a portion of the interlayer dielectric and the gate insulating layer to form a contact hole to a predetermined depth; and    wet etching the contact hole to complete the contact hole and expose a portion of the semiconductor layer.    
     
     
         8 . The method of  claim 7 , wherein the dry etching process includes any one of an ion etching process and a reactive etching process.  
     
     
         9 . The method of  claim 7 , further comprising removing a photoresist pattern before carrying out the wet etching that completes the contact hole.  
     
     
         10 . The method of  claim 7 , wherein the dry etching process includes at least one of a high etch rate dry etching process and a high selectivity dry etching process.  
     
     
         11 . A semiconductor device, comprising: 
 a substrate;    a thin film transistor (TFT) formed on the substrate and having a source electrode and a drain electrode;    a passivation layer and a planarization layer formed on the TFT; and    a via hole penetrating the passivation layer and the planarization layer and exposing a portion of either the source electrode and or the drain electrode, and having a multiple profile in which an upper portion of the via hole has a wet etch profile and a lower portion of the via hole has at least one of a wet etch profile and a dry etch profile.    
     
     
         12 . A method of fabricating a semiconductor device, comprising: 
 forming a thin film transistor (TFT) including a source electrode and a drain electrode on a substrate;    forming a passivation layer and a planarization layer on the TFT;    performing at least one of a dry etching process and a wet etching process on a portion of the passivation layer and the planarization layer to form a via hole to a predetermined depth; and    wet etching the via hole to complete the via hole and expose a portion of either the source electrode or the drain electrode.    
     
     
         13 . The method of  claim 12 , wherein the dry etching process includes any one of an ion etching process and a reactive etching process.  
     
     
         14 . The method of  claim 12 , further comprising removing a photoresist pattern before carrying out the wet etching that completes the contact hole.  
     
     
         15 . The method of  claim 12 , wherein the dry etching process includes at least one of a high etch rate dry etching process and a high selectivity dry etching process.  
     
     
         16 . A semiconductor device, comprising: 
 a substrate;    a metal interconnection line formed on the substrate;    an interlayer dielectric formed on the metal interconnection line; and    a via hole penetrating the interlayer dielectric and exposing a portion of the metal interconnection line, and having a multiple profile in which an upper portion of the via hole has a wet etch profile and a lower portion of the via hole has at least one of a wet etch profile and a dry etch profile.    
     
     
         17 . The semiconductor device of  claim 16 , further comprising an upper metal interconnection line contacting the metal interconnection line through the via hole.  
     
     
         18 . A method of fabricating a semiconductor device, comprising: 
 forming a metal interconnection line and an interlayer dielectric on a substrate;    performing at least one of a dry etching process and a wet etching process on a portion of the interlayer dielectric to form a via hole to a predetermined depth; and    wet etching the via hole to complete the via hole and expose a portion of the metal interconnection line.    
     
     
         19 . A semiconductor device, comprising: 
 a substrate;    a semiconductor layer, a gate insulating layer, and a gate electrode formed on the substrate;    a planarization layer formed on the substrate; and    a via contact hole penetrating the planarization layer and the gate insulating layer and exposing a portion of the semiconductor layer, and having a multiple profile in which an upper portion of the via contact hole has a wet etch profile and a lower portion of the via contact hole has at least one of a wet etch profile and a dry etch profile.    
     
     
         20 . The semiconductor device of  claim 19 , wherein a metal interconnection line or a pixel electrode contacts the exposed portion of the semiconductor layer through the via contact hole.  
     
     
         21 . A method of fabricating a semiconductor device, comprising: 
 forming a semiconductor layer, a gate insulating layer, and a gate electrode on a substrate;    forming a planarization layer on the substrate;    performing at least one of a dry etching process and a wet etching process on a portion of the gate insulating layer and the planarization layer to form a via contact hole to a predetermined depth; and    wet etching the via contact hole to complete the via contact hole and expose a portion of the semiconductor layer.    
     
     
         22 . A semiconductor device, comprising: 
 a substrate;    a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric formed on the substrate;    a thin film transistor (TFT) region including a contact hole, the contact hole penetrating the gate insulating layer and the interlayer dielectric, exposing a portion of the semiconductor layer, and having a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of a wet etch profile and a dry etch profile;    a metal interconnection line and an insulating layer formed on the substrate and spaced apart from the TFT region by a predetermined interval; and    a via hole penetrating the insulating layer and having a multiple profile in which an upper portion of the via hole has a wet etch profile and a lower portion of the via hole has at least one of a wet etch profile and a dry etch profile.    
     
     
         23 . The semiconductor device of  claim 22 , wherein an electrode contacts the exposed portion of the semiconductor layer through the contact hole, and an upper metal interconnection contacts the metal interconnection line through the via hole.  
     
     
         24 . A method of fabricating a semiconductor device, comprising: 
 forming a semiconductor layer, a gate insulating layer, and a gate electrode in a thin film transistor (TFT) region of a substrate;    forming a metal interconnection line in a metal interconnection line region spaced apart from the TFT region by a predetermined interval;    forming an interlayer dielectric in the TFT region, and forming an insulating layer in the metal interconnection line region;    performing at least one of a dry etching process and a wet etching process on a portion of the insulating layer in the metal interconnection line region, and on the interlayer dielectric and the gate insulating layer in the TFT region to form a contact hole having a predetermined depth in the TFT region and a via hole having a predetermined depth in the metal interconnection line region; and    wet etching the contact hole and the via hole to complete the contact hole and the via hole and expose a portion of the semiconductor layer in the TFT region and a portion of the metal interconnection line in the metal interconnection line region.    
     
     
         25 . A semiconductor device, comprising: 
 a substrate;    a thin film transistor formed on the substrate and including a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric; and    a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer, the contact hole including an upper portion having a first taper angle and a lower portion having a second taper angle,    wherein the second taper angle is steeper than the first taper angle.    
     
     
         26 . The semiconductor device of  claim 25 , wherein the upper portion of the contact hole is formed by wet etching and the first taper angle is in a range of about 5° to about 60°.  
     
     
         27 . The semiconductor device of  claim 25 , wherein the upper portion of the contact hole is formed by wet etching and the first taper angle is in a range of about 5° to about 45°.  
     
     
         28 . The semiconductor device of  claim 25 , wherein the lower portion of the contact hole is formed by dry etching and the second taper angle is in a range of about 60° to about 90°.  
     
     
         29 . The semiconductor device of  claim 25 , wherein the lower portion of the contact hole is formed by dry etching and the second taper angle is in a range of about 75° to about 90°.  
     
     
         30 . The semiconductor device of  claim 25 , wherein the contact hole further includes a lowest portion having a third taper angle, and the second taper angle is steeper than the third taper angle.  
     
     
         31 . A semiconductor device, comprising: 
 a substrate;    a thin film transistor (TFT) formed on the substrate and having a source electrode and a drain electrode;    a passivation layer and a planarization layer formed on the TFT; and    a via hole penetrating the passivation layer and the planarization layer and exposing a portion of either the source electrode and or the drain electrode, the via hole including an upper portion having a first taper angle and a lower portion having a second taper angle,    wherein the second taper angle is steeper than the first taper angle.    
     
     
         32 . A semiconductor device, comprising: 
 a substrate;    a metal interconnection line formed on the substrate;    an interlayer dielectric formed on the metal interconnection line; and    a via hole penetrating the interlayer dielectric and exposing a portion of the metal interconnection line, the via hole including an upper portion having a first taper angle and a lower portion having a second taper angle,    wherein the second taper angle is steeper than the first taper angle.    
     
     
         33 . The semiconductor device of  claim 32 , further comprising an upper metal interconnection line contacting the metal interconnection line through the via hole.  
     
     
         34 . A semiconductor device, comprising: 
 a substrate;    a semiconductor layer, a gate insulating layer, and a gate electrode formed on the substrate;    a planarization layer formed on the substrate; and    a via contact hole penetrating the planarization layer and the gate insulating layer and exposing a portion of the semiconductor layer, the via hole including an upper portion having a first taper angle and a lower portion having a second taper angle,    wherein the second taper angle is steeper than the first taper angle.    
     
     
         35 . The semiconductor device of  claim 34 , wherein a metal interconnection line or a pixel electrode contacts the exposed portion of the semiconductor layer through the via contact hole.  
     
     
         36 . A semiconductor device, comprising: 
 a substrate;    a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric formed on the substrate;    a thin film transistor (TFT) region including a contact hole, the contact hole penetrating the gate insulating layer and the interlayer dielectric, exposing a portion of the semiconductor layer, and including an upper portion having a first taper angle and a lower portion having a second taper angle;    a metal interconnection line and an insulating layer formed on the substrate and spaced apart from the TFT region by a predetermined interval; and    a via hole penetrating the insulating layer and including an upper portion having a third taper angle and a lower portion having a fourth taper angle,    wherein the second taper angle is steeper than the first taper angle, and    wherein the fourth taper angle is steeper than the third taper angle.    
     
     
         37 . The semiconductor device of  claim 36 , wherein an electrode contacts the exposed portion of the semiconductor layer through the contact hole, and an upper metal interconnection contacts the metal interconnection line through the via hole.