Integrated circuitry

Abstract

Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality of substantially identically shaped devices relative to the patterned device outlines. Individual formed devices are spaced from at least one other of the devices by a distance no more than a width of one of the electrically insulative spacers. In such manner, device pitch is reduced by almost fifty percent. According to one aspect, capacitors are formed which, according to a one embodiment, form part of a dynamic random access memory (DRAM) array.

1 - 41 . (canceled)  
   
   
       42 . Integrated circuitry comprising: 
 a substrate having a substrate surface;    a contact plug having an uppermost surface and extending through the substrate surface;    an outer pair of spacers disposed over the substrate surface, the outer pair of spacers comprising a first material;    an inner pair of spacers comprising a second material disposed along sidewalls of the outer pair of spacers and extending to a first elevation above the uppermost surface of the contact plug; and    a conductive material disposed between and in physical contact with the inner pair of spacers, the conductive material being in electrical contact with the contact plug and extending to a second elevation which is elevationally above the first elevation.    
   
   
       43 . The integrated circuitry of  claim 42  wherein the conductive material physically contacts the outer pair of spacers.  
   
   
       44 . The integrated circuitry of  claim 42  wherein at least one of the outer spacers is disposed along a sidewall of a polysilicon-comprising material.  
   
   
       45 . The integrated circuitry of  claim 44  wherein the polysilicon-comprising material is conductively doped polysilicon.  
   
   
       46 . The integrated circuitry of  claim 42  wherein the outer pair of spacers comprises a first spacer disposed along a sidewall of a polysilicon comprising material, and a second spacer disposed along a sidewall of a silicon nitride material.  
   
   
       47 . The integrated circuitry of  claim 46  wherein the silicon nitride material is comprised by a non-conductive partition, the non-conductive partition being between the second spacer and an electrically conductive container material.  
   
   
       48 . Integrated circuitry comprising: 
 a substrate having a plurality of nodes;    a plurality of bit line contacts associated with the nodes, each of the bit line contacts comprising: 
 an inner pair of dielectric sidewall spacers comprising a first material;  
 an outer pair of dielectric sidewall spacers in physical contact with the inner pair of dielectric spacers, the outer pair of dielectric sidewall spacers comprising a second material having a higher dielectric constant than the first material; and  
 a conductive material disposed between the spacers comprised by the inner pair of spacers and in electrical communication with the associated node.  
   
   
   
       49 . The integrated circuitry of  claim 48  wherein the first material comprises silicon dioxide.  
   
   
       50 . The integrated circuitry of  claim 48  wherein the second material comprises silicon nitride.  
   
   
       51 . The integrated circuitry of  claim 48  wherein the inner spacers are thicker than the outer spacers.  
   
   
       52 . The integrated circuitry of  claim 48  wherein the conductive material is a first conductive material, and wherein a first outer spacer comprised by the pair of outer spacers is in physical contact with a second conductive material.  
   
   
       53 . The integrated circuitry of  claim 52  wherein a second outer spacer comprised by the pair of outer spacers is disposed along a sidewall of a silicon nitride material.