Circuit layout and structure for a non-volatile memory

Abstract

A structure of non-volatile memory contains a substrate. A plurality of bit lines are formed in the substrate along a first direction, wherein each of the bit lines also serve as a source/drain (S/D) region. A first dielectric layer is disposed over the substrate. A plurality of selection gate (SG) lines are formed over the first dielectric layer between the bit lines. A plurality of charge-storage structure layer are formed over the substrate between the bit lines and the SG lines. A second dielectric layer is formed over the SG lines and a third dielectric layer is formed over the bit lines. A plurality of word lines are formed over the substrate along a second direction, which is crossing the first direction for the bit lines. Wherein, when a selected one of the SG lines is applied a voltage, another S/D region is created in the substrate under the selected one of the SG lines.

1 - 11 . (canceled)  
   
   
       12 . A circuit layout for a non-volatile memory device, comprising: 
 a plurality of MOS memory cells, arranged into rows and columns, wherein each of the MOS memory cells has two charge storage nodes commonly coupled with one selection gate (SG) line corresponding to the columns;    a plurality of buried bit lines coupled between adjacent two of the memory cells, to also serve as S/D electrodes of the memory cells;    a plurality of word lines, coupled to the memory cells with respect to the rows, also serve as gate electrodes of memory cells; and    a first and a second SG voltage feeding lines, wherein the SG lines are alternatively coupled to the first and the second SG voltage feeding lines,    wherein when the first SG voltage feeding line or the second SG voltage feeding line is applied with a activating voltage, a created S/D region occurs between the two charge storage nodes, so that a proper source voltage can be applied to the created S/D region to operate with the S/D electrode from the bit lines.    
   
   
       13 . The circuit layout of  claim 12 , wherein bank-select transistors are coupled between the bit lines and bit line voltage sources.  
   
   
       14 . The circuit layout of  claim 12 , wherein when a memory cell is selected, the SG line related to the selected memory cell is applied with the activating voltage while the adjacent SG line for the adjacent cells are set to a ground voltage.  
   
   
       15 . The circuit layout of  claim 14 , wherein all of the created S/D regions are coupled to a source voltage.  
   
   
       16 . The circuit layout of  claim 14 , wherein each of the first and the second SG voltage feeding lines is coupled to a gate electrode of a MOS transistor, and the MOS transistor has a first S/D electrode coupled to a source voltage, and a second S/D electrode coupled to all of the created S/D regions.  
   
   
       17 . The circuit layout of  claim 14 , wherein all of the created S/D regions are floating.  
   
   
       18 . The circuit layout of  claim 14 , wherein every two adjacent created S/D regions are grouped as one and coupled to a source voltage.  
   
   
       19 . The circuit layout of  claim 14 , wherein every four adjacent created S/D regions are grouped as one and coupled to a source voltage.  
   
   
       20 . A circuit layout for a non-volatile memory device, comprising: 
 a plurality of MOS memory cells, arranged into rows and columns, wherein each of the MOS memory cells has two charge storage nodes commonly coupled with one selection gate (SG) line corresponding to the columns;    a plurality of buried bit lines coupled between adjacent two of the memory cells, to also serve as S/D electrodes of the memory cells;    a plurality of word lines, coupled to the memory cells with respect to the rows, also serve as gate electrodes of memory cells; and    at least three SG voltage feeding lines, wherein the SG lines are alternatively coupled to the SG voltage feeding lines,    wherein three adjacent SG lines controlled by the SG voltage feeding lines are operated together to prevent a leakage to the adjacent memory cell, and when one of the SG voltage feeding lines is applied with a activating voltage, a created S/D region occurs between the two charge storage nodes.    
   
   
       21 . The circuit layout of  claim 20 , wherein the at least three SG voltage feeding lines is three SG voltage feeding lines, and one of the SG voltage feeding lines corresponding to the selected one of the memory cells is at the activating voltage while the other two are at ground voltage.  
   
   
       22 . The circuit layout of  claim 21 , wherein the unselected adjacent bit lines are set to a floating state.