Semiconductor device with self refresh test mode

Abstract

A semiconductor device (such as a DRAM) includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or controls various blocks and internal signals in the semiconductor device. The self refresh test mode controller may communicate with a remote testing device through various conductors including one or more DQ lines and/or one or more address lines. The self refresh test mode controller provides at least one or more of the following four functions: (1) the ability to control internal signals while in self refresh test mode; (2) the ability to monitor internal signals while in self refresh test mode; (3) the ability to put in a programmable delay, change the delay, or change internal timing while in self refresh test mode (add delay or make delay programmable, adjustable); (4) the ability to have the device do a device read in a self refresh test mode (the DQ pins may be used to read particular data on the row, while the column address is frozen).

1 . A semiconductor device having a memory array comprising: 
 an interface for receiving self refresh test control signals from an external device;    a self refresh test mode controller for outputting internal test control signals in response to the self refresh test control signals during a self refresh test mode of the semiconductor device, the self refresh test mode controller including circuitry for outputting indicating signals indicative of at least one of refresh signal through the interface to the external device;    self refresh circuitry for producing refresh signals including preliminary refresh signals and location refresh signals in response to the internal test control signals during the self refresh test mode of the semiconductor device, at least some of the preliminary refresh signals used in producing the location refresh signals; and    selection circuitry for selecting locations within the memory array to be refreshed in response to the location refresh signals.    
   
   
       2 . The semiconductor device of  claim 1 , wherein the indicating signals are indicative of one of the location refresh signals, the at least some of the preliminary refresh signals, and of at least some of the preliminary refresh signals and of the location refresh signals.  
   
   
       3 . The semiconductor device of  claim 1 , wherein the memory array includes rows and columns, and the locations within the memory array selected by the selection circuitry are rows.  
   
   
       4 . The semiconductor device of  claim 1 , wherein the refresh signals include one of row address strobe signals and column address strobe signals.  
   
   
       5 . The semiconductor device of  claim 1 , wherein the memory array is a first memory array, the self refresh circuitry is a first self refresh circuitry, and the self refresh test mode controller is a first self refresh test mode controller, and further comprising a second memory array, a second self refresh circuitry, and a second self refresh test mode controller, wherein the second memory array is refreshed in response to the second self refresh circuitry monitored by the second self refresh test mode controller.  
   
   
       6 . The semiconductor device of  claim 1 , wherein the interface includes at least one of address lines, DQ lines, and lines activated when the self refresh test mode controller is activated.  
   
   
       7 . The semiconductor device of  claim 1 , wherein the selection circuitry is one of directly responsive to the location refresh signals and indirectly responsive to the location refresh signals.  
   
   
       8 . The semiconductor device of  claim 1 , further comprising a sense amplifier and input/output gating assisting in a performance of the self refresh test mode.  
   
   
       9 . The semiconductor device of  claim 1 , wherein the self refresh circuitry includes at least one of a self refresh oscillator and timer and a refresh controller and a refresh counter.  
   
   
       10 . The semiconductor device of  claim 1 , wherein the selection circuitry includes a column decoder.  
   
   
       11 . The semiconductor device of  claim 1 , wherein the refresh signals include signals in addition to the preliminary refresh signals and the location refresh signals, the additional signals controlling various functions of self refresh.  
   
   
       12 . The semiconductor device of  claim 1 , wherein the self refresh circuitry and the self refresh test mode controller are each included in a microprocessor.  
   
   
       13 . A method for signals for self refreshing a memory array of a semiconductor device, the method comprising: 
 providing self refresh test control signals from an external testing device for controlling a self refresh test mode of the semiconductor device, the self refresh test control signals including at least some preliminary refresh signals and some location refresh signals;    producing refresh signals including the at least some preliminary refresh signals and the some location refresh signals in response to the self refresh test control signals, at least some of the at least some preliminary refresh signals used for producing the some location refresh signals;    selecting memory locations within the memory array to be refreshed in response to the some location refresh signals;    interacting with self refresh circuitry for providing indicating signals indicative of at least one of the refresh signals for controlling production of the refresh signals; and    analyzing the indicating signals for evaluating self refreshing of the memory array.    
   
   
       14 . A method for self refreshing operations of a semiconductor memory comprising: 
 using a Row Address Strobe (RAS) signal and a Column Address Strobe (CAS) signal for causing the semiconductor memory to enter a self refresh test mode;    self refreshing the semiconductor memory while the semiconductor memory is in the self refresh test mode;    outputting self refresh timing signals from a self refresh timer within the semiconductor memory by outputting row addresses from a self refresh counter of the semiconductor memory in response to the self refresh timing signals;    refreshing a row in a memory array of the semiconductor memory selected in accordance with row address thereof using a row decoder of the semiconductor memory; and    controlling the self refreshing of the semiconductor memory by providing at least one self refresh test mode control signal to the semiconductor memory from a testing device external to the semiconductor memory during the self refresh test mode of the semiconductor memory.    
   
   
       15 . The method of  claim 14 , wherein controlling the self refreshing of the semiconductor memory comprises controlling at least one of the self refresh timer, the self refresh counter, and the row decoder of the semiconductor memory using the self refresh test mode control signals.