Memory caching

Abstract

There are disclosed apparatus and methods for achieving maximum data transfer. Memories and interfaces between the memories are provided. An actively determined number of data units having an actively determined unit size are transferred between the memories to provide the maximum data transfer.

1 . An apparatus comprising: 
 a memory interface operable to transfer an actively-determined number of data units having an actively-determined unit size    a first memory having 
 a first input for receiving incoming data  
 a first output for transferring data units  
 a second output for transferring data units to the memory interface a second memory having  
 a second input for receiving data units from the memory interface  
 a third output for transferring data units a third memory having  
 a third input for receiving data units from the first output and the third output a fourth output for outputting data  
   wherein the actively determined number of data units having the actively determined unit size together provide a maximum memory transfer efficiency level for the memory interface.    
   
   
       2 . The apparatus of  claim 1  wherein 
 the data units comprise frames of variable length    the first memory stores data in at least one fixed size.    
   
   
       3 . The apparatus of  claim 1  wherein the maximum memory transfer efficiency level is achieved at least in part by maximizing an amount of data taken from the first memory and put in the data units.  
   
   
       4 . The apparatus of  claim 1  wherein the maximum memory transfer efficiency level is achieved at least in part by maximizing an amount of data destined for the third memory in the data units.  
   
   
       5 . The apparatus of  claim 1 , wherein the third memory further comprises a third memory fill indicator to indicate a fill characteristic of the third memory.  
   
   
       6 . The apparatus of  claim 5  wherein the third fill indicator further comprises 
 a first fill level wherein the determined number of data units having the determined unit size are transferred from the first memory to the third memory    a second fill level wherein the determined number of data units having the determined unit size are transferred from the first memory to the second memory via the memory interface    a third fill level wherein the determined number of data units having the determined unit size are transferred from the second memory to the third memory.    
   
   
       7 . The apparatus of  claim 1 , wherein the first memory further comprises a first memory fill indicator to indicate a fill characteristic of the first memory.  
   
   
       8 . The apparatus of  claim 7  wherein the first fill indicator further comprises 
 a first fill level wherein the determined number of data units having the determined unit size are transferred from the first memory to the third memory    a second fill level wherein the determined number of data units having the determined unit size are transferred from the first memory to the second memory via the memory interface.    
   
   
       9 . The apparatus of  claim 1 , wherein the incoming frames are of varying length and where the determined number of units are defined to include data from one or more of the frames, and wherein a determined unit may contain data from two or more frames.  
   
   
       10 . The apparatus of  claim 1 , wherein a data path to the second memory is wider than a width characteristic of the third memory.  
   
   
       11 . The apparatus of  claim 1 , wherein the first memory and third memory reside on a common semiconductor substrate, and wherein the second memory is remote to the semiconductor substrate.  
   
   
       12 . The apparatus of  claim 1  wherein the first memory and the third memory are selected from the group comprising first-in-first-out memories and data buffer memories.  
   
   
       13 . The apparatus of  claim 1  wherein the second memory is selected from the group comprising on-chip Dynamic Random Access Memories, off-chip Content-Addressable Memories and off-chip Static Random Access Memories.  
   
   
       14 . A method comprising: 
 actively determining a number of data units and a unit size to support a maximum efficiency level    transferring the determined number of data units having the determined unit size from the first memory to a second memory when the second memory is within a first fill level    transferring the determined number of data units having the determined unit size from the first memory to a third memory when the second memory is within a second fill level    transferring the determined number of data units having the determined unit size from the second memory to the third memory when the second memory is within a third fill level.    
   
   
       15 . The method of  claim 14  wherein 
 the data units include data from one or more frames of varying size    at least one data unit contains data from at least two frames.    
   
   
       16 . The method of  claim 14  wherein transferring the data units is based on a second memory fill indicator associated with the second memory.  
   
   
       17 . The method of  claim 14  wherein transferring the data units is based on a first memory fill indicator associated with the first memory.  
   
   
       18 . The method of  claim 14  wherein transferring the data units to the second memory includes controlling whether data units from the first memory or the third memory are transferred to the second memory.  
   
   
       19 . An apparatus comprising: 
 a first memory for receiving frames of varying amounts of incoming data    a second memory    a third memory coupled to the first memory and the second memory and operable to receive data either from the first memory or from the second memory    a controller coupled to the first memory, the second memory and the third memory and operable to control transfer of data    wherein an actively determined number of data units having an actively determined unit size is transferred between the first memory and the second memory and the third memory at a maximum memory transfer efficiency level.    
   
   
       20 . The apparatus of  claim 19  wherein 
 the data units comprise frames of variable length    the first memory stores data in at least one fixed size.    
   
   
       21 . The apparatus of  claim 19  wherein the maximum memory transfer efficiency level is achieved at least in part by maximizing an amount of data taken from the first memory and put in the data units.  
   
   
       22 . The apparatus of  claim 19  wherein the maximum memory transfer efficiency level is achieved at least in part by maximizing an amount of data destined for the third memory in the data units.  
   
   
       23 . The apparatus of  claim 19  wherein the third memory further comprises a third memory fill indicator to indicate a fill characteristic of the third memory.  
   
   
       24 . The apparatus of  claim 23  wherein the third fill indicator further comprises 
 a first fill level wherein the determined number of data units having the determined unit size are transferred from the first memory to the third memory    a second fill level wherein the determined number of data units having the determined unit size are transferred from the first memory to the second memory via the memory interface    a third fill level wherein the determined number of data units having the determined unit size are transferred from the second memory to the third memory.    
   
   
       25 . The apparatus of  claim 19 , wherein the first memory further comprises a first memory fill indicator to indicate a fill characteristic of the first memory.  
   
   
       26 . The apparatus of  claim 25  wherein the first fill indicator further comprises 
 a first fill level wherein the determined number of data units having the determined unit size are transferred from the first memory to the third memory    a second fill level wherein the determined number of data units having the determined unit size are transferred from the first memory to the second memory via the memory interface.    
   
   
       27 . The apparatus of  claim 19  wherein the incoming frames are of varying length and where the determined number of units are defined to include data from one or more of the frames, and wherein a determined unit may contain data from two or more frames.  
   
   
       28 . The apparatus of  claim 19  wherein a data path to the second memory is wider than a width characteristic of the third memory.  
   
   
       29 . The apparatus of  claim 19  wherein the first memory and third memory reside on a common semiconductor substrate, and wherein the second memory is remote to the semiconductor substrate.  
   
   
       30 . The apparatus of  claim 19  wherein the first memory and the third memory are selected from the group comprising first-in-first-out memories and data buffer memories.  
   
   
       31 . The apparatus of  claim 19  wherein the second memory is selected from the group comprising on-chip Dynamic Random Access Memories, off-chip Content-Addressable Memories and off-chip Static Random Access Memories.  
   
   
       32 . A method comprising: 
 transferring an actively determined number of data units having an actively determined unit size from a first memory to a second memory, the first memory having an input to receive frames containing varying amounts of data and the second memory having an output to output data    transferring the actively determined number of data units having the actively determined unit size from the first memory to a third memory via a memory interface    transferring the actively determined number of data units having the actively determined unit size from the third memory to the second memory    wherein the actively determined unit size and the actively determined number of data units together provide a maximum memory transfer efficiency level for the memory interface.    
   
   
       33 . The method of  claim 32  wherein 
 the data units include data from one or more frames of varying size    at least one data unit contains data from at least two frames.    
   
   
       34 . The method of  claim 32  wherein transferring the data units is based on a second memory fill indicator associated with the second memory.  
   
   
       35 . The method of  claim 34  wherein transferring the data units further comprises 
 transferring the data units from the first memory to the second memory at a first fill level    transferring the data units from the first memory to the third memory at a second fill level    transferring the data units from the third memory to the second memory at a third fill level    
   
   
       36 . The method of  claim 32  wherein transferring the data units is based on a first memory fill indicator associated with the first memory.  
   
   
       37 . The method of  claim 36  wherein transferring the data units further comprises 
 transferring the data units from the first memory to the second memory at a first fill level    transferring the data units from the first memory to the third memory at a second fill level    
   
   
       38 . The method of  claim 32  wherein transferring the data units to the second memory includes controlling whether data units from the first memory or the third memory are transferred to the second memory.  
   
   
       39 . An apparatus comprising: 
 a first memory    a second memory    a memory interface 
 coupled to the first memory and to the second memory  
 operable to copy an actively determined number of data units having an actively determined unit size from the first memory to the second memory  
   wherein the determined unit size and the determined number of data units together provide maximum memory transfer efficiency.    
   
   
       40 . The apparatus of  claim 39  wherein 
 the data units comprise frames of variable length    the first memory stores data in at least one fixed size.    
   
   
       41 . The apparatus of  claim 39  wherein the maximum memory transfer efficiency level is achieved at least in part by maximizing an amount of data taken from the first memory and put in the data units.  
   
   
       42 . The apparatus of  claim 39  wherein the maximum memory transfer efficiency level is achieved at least in part by maximizing an amount of data in the data units destined for output.  
   
   
       43 . The apparatus of  claim 39  further comprising a third memory coupled to the first memory and the second memory.  
   
   
       44 . The apparatus of  claim 43  further comprising a third memory fill indicator to indicate a fill characteristic.  
   
   
       45 . The apparatus of  claim 44  wherein the third memory fill indicator further comprises 
 a first fill level wherein the determined number of data units having the determined unit size are transferred from the first memory to the third memory    a second fill level wherein the determined number of data units having the determined unit size are transferred from the first memory to the second memory via the memory interface    a third fill level wherein the determined number of data units having the determined unit size are transferred from the second memory to the third memory.    
   
   
       46 . The apparatus of  claim 39  wherein the first memory further comprises a first memory fill indicator to indicate a fill characteristic.  
   
   
       47 . The apparatus of  claim 39  wherein the first memory fill indicator further comprises 
 a first fill level wherein the determined number of data units having the determined unit size are outputted from the first memory.    a second fill level wherein the determined number of data units having the determined unit size are transferred from the first memory to the second memory via the memory interface.    
   
   
       48 . The apparatus of  claim 39 , wherein the incoming frames are of varying length and where the determined number of units are defined to include data from one or more of the frames, and wherein a determined unit may contain data from two or more frames.  
   
   
       49 . The apparatus of  claim 43 , wherein a data path to the second memory is wider than a width characteristic of the third memory.  
   
   
       50 . The apparatus of  claim 43 , wherein the first memory and third memory reside on a common semiconductor substrate, and wherein the second memory is remote to the semiconductor substrate.  
   
   
       51 . The apparatus of  claim 39  wherein the first memory is selected from the group comprising first-in-first-out memories and data buffer memories.  
   
   
       52 . The apparatus of  claim 39  wherein the second memory is selected from the group comprising on-chip Dynamic Random Access Memories, off-chip Content-Addressable Memories and off-chip Static Random Access Memories.  
   
   
       53 . The apparatus of  claim 43  wherein the third memory is selected from the group comprising first-in-first-out memories and data buffer memories.