High dielectric constant spacer for imagers

Abstract

An imager having gates with spacers formed of a high dielectric material. The high dielectric spacer provides larger fringing fields for charge transfer and improves image lag and charge transfer efficiency.

1 . A pixel sensor cell comprising: 
 a photoconversion device; and    at least one gate stack, said at least one gate stack having at least one portion covered by a spacer layer comprising high dielectric constant material.    
   
   
       2 . The pixel sensor cell of  claim 1 , wherein said high dielectric material is selected from the group consisting of metal oxide, aluminum oxide, hafnium oxide, tantalum oxide, silicon nitride and barium strontium titanate.  
   
   
       3 . The pixel sensor cell of  claim 1 , wherein said at least one gate stack is part of a transistor selected from the group consisting of a transfer transistor, storage transistor, high dynamic range transistor, source follower transistor, row select transistor and a global shutter transistor.  
   
   
       4 . The pixel sensor cell of  claim 3 , wherein said transistor is part of a pixel sensor cell selected from the group consisting of a four transistor, five transistor, six transistor and seven transistor pixel sensor cell.  
   
   
       5 . The pixel sensor cell of  claim 1 , wherein said pixel sensor cell is part of a CCD sensor.  
   
   
       6 . The pixel sensor cell of  claim 5 , wherein the CCD sensor is a single gate CCD sensor.  
   
   
       7 . The pixel sensor cell of  claim 5 , wherein the CCD sensor is an overlapping gate sensor.  
   
   
       8 . The pixel sensor cell of  claim 1 , wherein the photoconversion device is selected from the group consisting of a photodiode, a photogate and a photosensor.  
   
   
       9 . The pixel sensor cell of  claim 8 , wherein said photodiode is a pnp photodiode.  
   
   
       10 . The pixel sensor cell of  claim 8 , wherein said photodiode is an npn photodiode.  
   
   
       11 . The pixel sensor cell of  claim 1 , wherein said gate stack is part of an n-channel transistor.  
   
   
       12 . The pixel sensor cell of  claim 1 , wherein said gate stack is part of a p-channel transistor.  
   
   
       13 . The pixel sensor cell of  claim 1 , wherein said gate stack is formed of a gate oxide layer and a conductor layer.  
   
   
       14 . The pixel sensor cell of  claim 1 , wherein said gate stack is formed of a gate oxide layer, a conductor layer and an insulator layer.  
   
   
       15 . The pixel sensor cell of  claim 13 , wherein said conductor layer is formed of at least one of poly, poly/silicide, poly WSix, poly/TiSix, poly/metal and poly/WNx/W.  
   
   
       16 . The pixel sensor cell of  claim 14 , wherein said insulator layer is formed of at least one of oxide, nitride, aluminum oxide, hafnium oxide, tantalum oxide and BST.  
   
   
       17 . The pixel sensor cell of  claim 13 , wherein said gate oxide layer is a grown layer.  
   
   
       18 . The pixel sensor cell of  claim 17  wherein said grown oxide layer is formed of at least one of silicon oxide, silicon nitride, and silicon oxide/silicon nitride.  
   
   
       19 . The pixel sensor cell of  claim 13 , wherein said gate oxide layer is a deposited layer.  
   
   
       20 . The pixel sensor cell of  claim 19 , wherein said deposited oxide layer is formed of at least one of nitride, metal oxide, aluminum oxide, hafnium oxide, tantalum oxide and BST.  
   
   
       21 . The pixel sensor cell of  claim 1 , wherein said high dielectric constant material spacer has a thickness of about 100 Åto about 1500 Å.  
   
   
       22 . The pixel sensor cell of  claim 1 , wherein said high dielectric constant material spacer has a thickness of about 200 Å to about 800 Å.  
   
   
       23 . The pixel sensor cell of  claim 1 , wherein said pixel sensor cell is part of a CMOS imager.  
   
   
       24 . An imager integrated circuit comprising: 
 a doped layer formed in a substrate;    an array of pixel sensor cells formed in said doped layer, wherein each pixel sensor cell has at least one gate stack, said at least one gate stack having at least one portion covered by a spacer layer of high dielectric constant material; and    signal processing circuitry formed in said substrate and electrically connected to the array for receiving and processing pixel signals representing an image acquired by the array and for providing output data representing said image.    
   
   
       25 . The imager integrated circuit of  claim 24 , wherein said high dielectric material is selected from the group consisting of metal oxide, aluminum oxide, hafnium oxide, tantalum oxide, silicon nitride and barium strontium titanate.  
   
   
       26 . The imager integrated circuit of  claim 24 , wherein said at least one gate stack is part of a transistor selected from the group consisting of a transfer transistor, storage transistor, high dynamic range transistor, source follower transistor, row select transistor and a global shutter transistor.  
   
   
       27 . The imager integrated circuit of  claim 26 , wherein said transistor is part of a pixel sensor cell selected from the group consisting of a four transistor, five transistor, six transistor and seven transistor pixel sensor cell.  
   
   
       28 . The imager integrated circuit of  claim 24 , wherein said pixel sensor cell is part of a CCD sensor.  
   
   
       29 . The imager integrated circuit of  claim 28 , wherein the CCD sensor is a single gate CCD sensor.  
   
   
       30 . The imager integrated circuit of  claim 28 , wherein the CCD sensor is an overlapping gate sensor.  
   
   
       31 . The imager integrated circuit of  claim 24 , wherein the photoconversion device is selected from the group consisting of a photodiode, a photogate and a photosensor.  
   
   
       32 . The imager integrated circuit of  claim 31 , wherein said photodiode is a pnp photodiode.  
   
   
       33 . The imager integrated circuit of  claim 31 , wherein said photodiode is an npn photodiode.  
   
   
       34 . The imager integrated circuit of  claim 24 , wherein said gate stack is part of an n-channel transistor.  
   
   
       35 . The imager integrated circuit of  claim 24 , wherein said gate stack is part of a p-channel transistor.  
   
   
       36 . The imager integrated circuit of  claim 24 , wherein said gate stack is formed of a gate oxide layer and a conductor layer.  
   
   
       37 . The imager integrated circuit of  claim 24 , wherein said gate stack is formed of a gate oxide layer, a conductor layer and an insulator layer.  
   
   
       38 . The imager integrated circuit of  claim 36 , wherein said conductor layer is formed of at least one of poly, poly/silicide, poly WSix, poly/TiSix, poly/metal and poly/WNx/W.  
   
   
       39 . The imager integrated circuit of  claim 37 , wherein said insulator layer is formed of at least one of oxide, nitride, aluminum oxide, hafnium oxide, tantalum oxide and BST.  
   
   
       40 . The imager integrated circuit of  claim 36 , wherein said gate oxide layer is a grown layer.  
   
   
       41 . The imager integrated circuit of  claim 40 , wherein said grown oxide layer is formed of at least one of silicon oxide, silicon nitride, and silicon oxide/silicon nitride.  
   
   
       42 . The imager integrated circuit of  claim 36 , wherein said gate oxide layer is a deposited layer.  
   
   
       43 . The imager integrated circuit of  claim 42 , wherein said deposited oxide layer is formed of at least one of nitride, metal oxide, aluminum oxide, hafnium oxide, tantalum oxide and BST.  
   
   
       44 . The imager integrated circuit of  claim 24 , wherein said high dielectric constant material spacer has a thickness of about 100 Å to about 1500 Å.  
   
   
       45 . The imager integrated circuit of  claim 24 , wherein said high dielectric constant material spacer has a thickness of about 200 Å to about 800 Å.  
   
   
       46 . The imager integrated circuit of  claim 24 , wherein said pixel sensor cell is part of a CMOS imager.  
   
   
       47 . A processing system comprising: 
 a processor; and    an imager coupled to said processor, having pixel sensor cells, wherein each pixel sensor cell has at least one gate stack, said at least one gate stack having at least one portion covered by a spacer layer of high dielectric constant material.    
   
   
       48 . The system of  claim 47 , wherein said high dielectric material is selected from the group consisting of metal oxide, aluminum oxide, hafnium oxide, tantalum oxide, silicon nitride and barium strontium titanate.  
   
   
       49 . The system of  claim 47 , wherein said at least one gate stack is part of a transistor selected from the group consisting of a transfer transistor, storage transistor, high dynamic range transistor, source follower transistor, row select transistor and a global shutter transistor.  
   
   
       50 . The system of  claim 49 , wherein said transistor is part of a pixel sensor cell selected from the group consisting of a four transistor, five transistor, six transistor and seven transistor pixel sensor cell.  
   
   
       51 . The system of  claim 47 , wherein said pixel sensor cell is part of a CCD sensor.  
   
   
       52 . The system of  claim 51 , wherein the CCD sensor is a single gate CCD sensor.  
   
   
       53 . The system of  claim 51 , wherein the CCD sensor is an overlapping gate sensor.  
   
   
       54 . The system of  claim 47 , wherein the photoconversion device is selected from the group consisting of a photodiode, a photogate and a photo sensor.  
   
   
       55 . The system of  claim 54 , wherein said photodiode is a pnp photodiode.  
   
   
       56 . The system of  claim 54 , wherein said photodiode is an npn photodiode.  
   
   
       57 . The system of  claim 47 , wherein said gate stack is part of an n-channel transistor.  
   
   
       58 . The system of  claim 47 , wherein said gate stack is part of a p-channel transistor.  
   
   
       59 . The system of  claim 47 , wherein said gate stack is formed of a gate oxide layer and a conductor layer.  
   
   
       60 . The system of  claim 47 , wherein said gate stack is formed of a gate oxide layer, a conductor layer and an insulator layer.  
   
   
       61 . The system of  claim 59 , wherein said conductor layer is formed of at least one of poly, poly/silicide, poly WSix, poly/TiSix, poly/metal and poly/WNx/W.  
   
   
       62 . The system of  claim 60 , wherein said insulator layer is formed of at least one of oxide, nitride, aluminum oxide, hafnium oxide, tantalum oxide and BST.  
   
   
       63 . The system of  claim 59 , wherein said gate oxide layer is a grown layer.  
   
   
       64 . The system of  claim 63 , wherein said grown oxide layer is formed of at least one of silicon oxide, silicon nitride, and silicon oxide/silicon nitride.  
   
   
       65 . The system of  claim 59 , wherein said gate oxide layer is a deposited layer.  
   
   
       66 . The system of  claim 65 , wherein said deposited oxide layer is formed of at least one of nitride, metal oxide, aluminum oxide, hafnium oxide, tantalum oxide and BST.  
   
   
       67 . The system of  claim 47 , wherein said high dielectric constant material spacer has a thickness of about 100 Å to about 1500 Å.  
   
   
       68 . The system of  claim 47 , wherein said high dielectric constant material spacer has a thickness of about 200 Å to about 800 Å.  
   
   
       69 . The system of  claim 47 , wherein said pixel sensor cell is part of a CMOS imager.  
   
   
       70 . A method of forming a pixel sensor cell comprising: 
 forming at least one gate stack;    forming a spacer over at least one portion of said at least one gate stack, wherein said spacer is comprised of a high dielectric constant material.    
   
   
       71 . The method of  claim 70 , wherein said forming a spacer step comprises forming the spacer with a thickness of about 100 Å to about 1500 Å.  
   
   
       72 . The method of  claim 70 , wherein said forming a spacer step comprises forming the spacer with a thickness of about 200 Å to about 600 Å.  
   
   
       73 . The method of  claim 70 , further comprising etching said spacer layer.  
   
   
       74 . The method of  claim 73 , wherein said pixel sensor cell is masked before said etching step.  
   
   
       75 . The method of  claim 70 , wherein said high dielectric material is selected from the group consisting of metal oxide, aluminum oxide, hafnium oxide, tantalum oxide, silicon nitride and barium strontium titanate.  
   
   
       76 . The method of  claim 70 , wherein said at least one gate stack is part of a transistor selected from the group consisting of a transfer transistor, storage transistor, high dynamic range transistor, source follower transistor, row select transistor and a global shutter transistor.  
   
   
       77 . The method of  claim 76 , wherein said transistor is part of a pixel sensor cell selected from the group consisting of a four transistor, five transistor, six transistor and seven transistor pixel sensor cell.  
   
   
       78 . The method of  claim 70 , wherein said pixel sensor cell is part of a CCD sensor.  
   
   
       79 . The method of  claim 78 , wherein the CCD sensor is a single gate CCD sensor.  
   
   
       80 . The method of  claim 78 , wherein the CCD sensor is an overlapping gate sensor.  
   
   
       81 . The method of  claim 70 , wherein said gate stack is part of an n-channel transistor.  
   
   
       82 . The method of  claim 70 , wherein said gate stack is part of a p-channel transistor.  
   
   
       83 . The method of  claim 70 , wherein said gate stack is formed of a gate oxide layer and a conductor layer.  
   
   
       84 . The method of  claim 70 , wherein said gate stack is formed of a gate oxide layer, a conductor layer and an insulator layer.  
   
   
       85 . The method of  claim 84 , wherein said conductor layer is formed of at least one of poly, poly/silicide, poly WSix, poly/TiSix, poly/metal and poly/WNx/W.  
   
   
       86 . The method of  claim 84 , wherein said insulator layer is formed of at least one of oxide, nitride, aluminum oxide, hafnium oxide, tantalum oxide and BST.  
   
   
       87 . The method of  claim 83 , wherein said gate oxide layer is a grown layer.  
   
   
       88 . The method of  claim 87 , wherein said grown oxide layer is formed of at least one of silicon oxide, silicon nitride, and silicon oxide/silicon nitride.  
   
   
       89 . The method of  claim 83 , wherein said gate oxide layer is a deposited layer.  
   
   
       90 . The method of  claim 89 , wherein said deposited oxide layer is formed of at least one of nitride, metal oxide, aluminum oxide, hafnium oxide, tantalum oxide and BST.  
   
   
       91 . The method of  claim 70 , wherein said high dielectric constant material spacer has a thickness of about 100 Å to about 1500 Å.  
   
   
       92 . The method of  claim 70 , wherein said high dielectric constant material spacer has a thickness of about 200 Å to about 800 Å.  
   
   
       93 . The method of  claim 70 , wherein said pixel sensor cell is part of a CMOS imager.